Kartik Shah

🤩Exciting news out of India as the country takes a major leap forward in chip manufacturing with the approval of its first commercial chip fabrication plant! Read on with this insightful article.

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You're pretty well understood, cost is a crucial factor for GaN HEMTs to gain wider adoption. While they offer significant performance advantages, their price point has historically been a barrier to entry. A simplified cost breakdown table comparing the cost of a silicon-based solution to a GaN-based solution for a 10kW motor drive system, and for a 1kW, 1MHz DC-DC converter. Key Takeaways: - Power Stage: The most significant cost component in a motor drive system as well as a DC-DC converter. GaN HEMTs offer a significant cost reduction in this area due to their smaller size, higher efficiency, and reduced need for complex cooling solutions. - Control Board: The cost is similar for both silicon and GaN solutions, as the control algorithms are independent of the power stage technology. - Magnetic Components (for DC-DC converter): GaN HEMTs' higher switching frequencies allow for smaller and less expensive magnetic components (inductors and transformers) in the converter. - Cooling System: GaN HEMTs generate less heat, leading to smaller and less expensive cooling systems compared to silicon MOSFETs. - Other Components: The cost of other components, like sensors and connectors, is relatively similar for both solutions. Notes: - The cost numbers in the table are not real costs but rather base references used for comparison. - The cost analysis is an essential part of any design process. It's crucial to consider the total cost of ownership (TCO), including initial cost, operating cost, and maintenance cost, when making technology choices. The future of GaN HEMTs looks bright, with the potential to revolutionize various industries by offering superior performance and efficiency at a competitive price. Short Term (Next 2-3 Years): - GaN HEMTs are already cost-effective in niche applications like high-power, high-frequency converters, where their performance advantages outweigh the initial cost premium. - GaN will likely see increased adoption in sectors like electric vehicles, renewable energy, and data centers, where efficiency and size reduction are critical. - Manufacturing costs will continue to decrease as production scales up and packaging technologies improve. Mid-Term (Next 5-7 Years): - GaN HEMTs will start to penetrate broader markets, including consumer electronics, industrial automation, and medical devices. - GaN HEMTs will become price-competitive with silicon MOSFETs in many applications, especially in higher power ranges. - More engineers and designers will gain experience with GaN, leading to more innovative applications and further cost reductions. —————————————————————- Dear friends and connections, I would like to find myself at the beginning of a new chapter. I am seeking new job opportunities where I can continue to drive advancements and crafting the future of semiconductor. Thank you for your support and any leads you can provide.

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Advanced Packaging Is Radically Reshaping the #Chip Ecosystem 💡 Periodically, analysts commenting on the chip industry will pronounce that Moore’s Law is obsolete. Yet while the speed of progress is slowing down, #chipmakers are still doubling the number of #transistors on an integrated circuit (#IC) approximately every 2.5 years. In the past, fundamentally new approaches for chip design never seemed to catch on. That’s no longer the case as fresh ideas that are essential for running some of today’s most important applications are rapidly gaining favor. One of the most significant of these new concepts is #advancedpackaging, which essentially accommodates an ever-increasing number of transistors by decreasing the size of electrical contacts. Traditionally, a #semiconductor chip focuses on performing one particular action or process. By comparison, an advanced multichip package incorporates multiple chips and processes into one component. This transformative approach integrates a multitude of semiconductor components into a single package, directly addressing the most critical semiconductor technical and commercial constraints. A very big thank you to my friend Dr. Karl Breidenbach and his colleagues Joseph Fitzgerald, Jan H. Mohr, Dr. Nadim Sah, Dr. Jörg Jeschke, Dr. Karl Breidenbach, Nicola Kerschbaumer,  Sohini Kar from Boston Consulting Group (BCG) for the full article with more background, charts and insights via the link below 💡🙏👇 https://lnkd.in/eVvUhbKf #semicondcutorindustry #semiconductors #semiconductor #chip #ic #technology #tech #chiplets #chiplet #foundry #innovation #icdesign #tsmc #samsung #intel #geopolitics #usa #taiwan #southkorea #it #ai

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While a basic concept, the Calibre nmDRC Recon use model of Calibre Real-time Digital is a unique approach that drives a significant improvement in overall verification turn around time. It also puts the data to quickly fix DRC errors in the hands of the teams that can best do that. Check it out and see first yourself.

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A very interesting blog by Giuseppe Piccolboni of Weebit Nano Ltd about the use of our #ReRAM for #neuromorphic applications

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Sahita Technologies is dedicated to empowering companies and nations to gain a competitive edge in the semiconductor and manufacturing sectors. Our comprehensive consulting services encompass: 🔧 Advanced Manufacturing ✅ Quality Assurance 🚚 Supply Chain Optimization 👩‍🏭 Workforce Development 🛠️ Framework Development 🎥 Semiconductor Workforce Documentary Join us in driving the smart manufacturing revolution! We specialize in creating robust semiconductor and manufacturing frameworks, strategic workforce solutions, and fostering vital industry-academic collaborations. 🤝 We're at the forefront of integrating technology and media to engage the next generation of students and professionals. 🚀 Join us in shaping the future of manufacturing and semiconductors! Together, we can drive innovation, excellence, and growth. Current engagements: ▪University of Texas at Dallas - Build workforce strategy for the North Texas Semiconductor Institute ▪Consult with research firms and investors on current needs and future trends ▪Partner: SRC Semiconductor Manufacturing and Advanced Research with Twins (SMART) USA Institute ▪Industry-Academia Collaborations: Fostering partnerships between educational institutions and the semiconductor industry. #Semiconductors #Manufacturing #WorkforceDevelopment #SmartManufacturing https://lnkd.in/gQvH3fwT

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#Chipmaking to go subzero — 3D #flashmemory manufactured at -70C with next-gen tool 💡SK hynix is reportedly testing cryogenic etching 🤩 SK hynix is evaluating TOKYO ELECTRON LIMITED (TEL) latest cryogenic etching tools, which operate at -70C temperatures, to enable new flavors of 3D #NAND with more than 400 layers. Cryogenic #etching tools 'drill holes' three times faster than conventional tools, a capability that will be instrumental for 3D NAND with over 400 active layers, reports The Elec. Instead of importing the actual equipment to #SouthKorea, SK hynix is sending test #wafers to Tokyo Electron labs in #Japan. This method enables the 3D NAND maker to effectively assess the #technology's potential without shipping actual tools to SK Hynix and installing them into fabs. The new etching system operates at a chilling temperature of -70°C, which is a stark contrast to the 0°C to 30°C range of current etching processes. A big thank you again to Anton Shilov and Tom's Hardware for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eyuB4kbn #semiconductorindustry #semiconductors #semiconductor #technology #tech #chips #computing #ai #semiconductormanufacturing #innovation

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PHELOS Gonio-Spectrometer for Angle-Dependent EL and PL Measurements Phelos is an angular luminescence spectrometer to characterize light-emitting devices and thin films over varied emission and polarization angles. While traditional goniometric instruments focus on either electroluminescence (EL) or photoluminescence (PL), Phelos incorporates both measuring techniques in one table-top compact instrument. The Phelos software can be easily coupled to the powerful simulation software Setfos for data analysis, parameter extraction, and device modeling. #SOLARCELL #PEROVSKITE #OLED #PVSOLARCELL

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TSMC and Cadence are collaborating on next-generation #AI-driven flows, including the Cadence Cerebrus™ Intelligent Chip Explorer, for design productivity and optimization and Pegasus™ Verification System for Physical verification Signoff. #Cadence #Signoff #PhysicalVerification #Design #FoundryCertified “We have a distinguished track record collaborating with TSMC to deliver a broad set of innovations across EDA, packaging and IP to accelerate system and semiconductor design and enable customers to achieve aggressive time-to-market goals. These new certified design flows and standardized solutions allow customers to confidently design for TSMC advanced nodes and usher in improved design efficiency and technological advancements,” said Chin-Chi Teng, SVP and GM, R&D, Cadence. Read the press release here: https://ow.ly/bTym50REHjG

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Billions of dollars have been pouring into the semiconductor industry in the U.S. thanks to #CHIPS funding, but the success of the CHIPS and Science Act not only hinges on funding, but the talent working on creating and maximizing opportunities created by all that funding. According to a new report from McKinsey, more than 17,000 jobs will be created through the expanded operations spurred by CHIPS funding and addressing those talent needs will be key to meeting the surge in demand that is coming as a result of the construction of new fabs and other facilities across the country. IQE’s CTO Rodney Pelzel says the industry needs a new breed of engineer to meet the #workforce needs of today, particularly engineers who go through a re-imagined undergraduate experience. But, perhaps we need to take this back even further and reimagine #STEM education at the K-12 level to make sure our CHIPS stay on track. Check out the full report from McKinsey here:

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Applied is the AI enabler👍

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How Paios was used Paios was utilized for comprehensive electrical characterization, including space-charge-limited current measurements, electrochemical impedance spectroscopy, capacitance-voltage analysis, and transient electroluminescence studies. These tests revealed that the additives effectively reduced trap densities and leakage currents, improved carrier transport, and enhanced charge transfer efficiency, corroborating the additives' impact on device performance and stability. more information visit here :- https://lnkd.in/d_D-Aifd #Solarcell #perovskite #oled #semicunductordevice

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TNL-EpiGrow simulator: Example MBE epitaxy of group IV, IV-IV, III-V, II-VI etc. HgCdTe (MCT) Epitaxial MBE Growth Solution, published in Journal of Electronic Materials . TNL-EpiGrow simulator will surely help to diagnose the formation of various defects, strain etc. The solution to obtain the crystalline MCT film USER can do optimization of MBE process input parameters through simulation. Hit & trail with different substrate options to reduce the cost associated with MCT epitaxy. For more details: https://rdcu.be/dFtco #MBE, #MOVPE, #MOCVD, #MCT, #Narrowbandgap, #Defects, #thinfilm, #Roughness, #LatticeParameter, #Epitaxy, #Growth, #ThinFilm, #HgCdTe, #Infrared, #Detector, #CdTe, #Si, #GaSb, #GaAs, #QuantumWell, #Nanosheet, #Optoelectronics, #Qualcomm, #Huawei, #IMEC, #IBM, #Intel, #Samsung, #WinSemiconductor, #TSMC, #GF, #TEL, #Wafer, #EpiWafer, #Vacancies, #dislocation, #TDD, #Crystalline, #Reactor, #GrowthRate, #Silvaco, #Synopsis, #EPIR, #Teledyne, #NASA, #DARPA, #CEALETI, #IME, #IMRI, #IHPC, #EPIR, #DRDO, #ISRO, #Defence, #NightVision, #Thermal, #Imaging, #IR, #MWIR, #LWIR, #SWIR, #T2SL, #HOT, #SMIC, #IIT, #IISC, #Teledyne, #E2V, #DRS, #LEONARDO, #ShivananthanLab, #IllinoisUniversity, #Meity, #PMO

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TECH NEXT LAB is presenting MOCVD/MOVPE epitaxy solutions of Group III-V Nitrides at 21st International Conference on Metal Organic Vapor Phase Epitaxy (ICMOVPE), to be held at Nevada during 12-17 May, 2024. https://lnkd.in/gvhHW28v   1.      Control ID: 4072524 Final ID: 1D-2.3 Abstract Title: Epitaxy of III-V Nitrides with Strain Relief Layers Analysis—TNL EpiGrow Simulator Session: 1D-2: Nitride Power Device/HEMT Session Date and Time: May 13, 2024 from 4:00 PM to 5:10 PM Las Vegas Local Time Presentation Time: 4:50 PM to 5:10 PM Las Vegas Local Time 2.      Event organized by Tech Next Lab: Optimization of MOVPE/MOCVD Epitaxy through Atomistic Simulation to reduce Cost May 14, 2024 from 6:00 PM to 6:30 PM Las Vegas Local Time 3.      Control ID: 4072473 Final ID: 5B-2.1 Abstract Title: MOCVD/MOVPE Epitaxy Solution of Group III-V Nitride with Atomistic Prospective and Cost Effectiveness Session: 5B-2: Fundamental Studies/Modeling of Epitaxy Session Date and Time: May 17, 2024 from 10:30 AM to 12:50 PM Las Vegas Local Time Presentation Time: 10:30 AM to 10:50 AM Las Vegas Local Time Please join me and let us discuss your MOCVD/MOVPE reactor epitaxial growth of Group III – V Nitrides related issues and challenges. Solution through atomistic TNL-EpiGrow simulator use to optimize the epitaxy process. In turn, reduce the experimentation cost, manpower consumption, and time of development cycle.  https://lnkd.in/gBtfTr3n #MBE, #MOVPE, #MOCVD, #Powerdevice, #GaN, #SiC, #InN, #AlN, #AlGaN, #InAlN, #InGaN, #ICMOVPE, #MRS, #Solarcell, #Diamond, #Ga2O3, #OXIDE, #UCB, #Stanford, #TI, #Hitachi, #SOITEC, #SMIC, #GF, #TSMC, #Micron, #UMC, #Infineon, #IME, #IMRI, #ASTAR, #ELI, #Widebandgap, #Defects, #thinfilm, #Roughness, #LatticeParameter, #Epitaxy, #Growth, #ThinFilm, #GaN, #Si, #GaSb, #GaAs, #QuantumWell, #Nanosheet, #Optoelectronics, #Qualcomm, #Huawei, #IMEC, #IBM, #Intel, #Samsung, #WinSemiconductor, #TSMC, #GF, #TEL, #Wafer, #EpiWafer, #Vacancies, #dislocation, #TDD, #Crystalline, #Reactor, #GrowthRate, #EPIR, #Teledyne, #NASA, #DARPA, #CEALETI, #IME, #IMRI, #IHPC, #EPIR, #DRDO, #ISRO, #Defence, #NightVision, #Thermal, #Imaging, #IR, #MWIR, #LWIR, #SWIR, #T2SL, #HOT, #SMIC, #IIT, #IISC, #Teledyne, #E2V, #DRS, #LEONARDO, #ShivananthanLab, #IllinoisUniversity, #QuinasULTRARAM, #intelliepi, #STMicro, #Meity, #PMO, #ICMOVPE, #SOITEC, #MIZOUniv, #GeorgiaTech, #NYMCTU, #Hokkaido, #UTA, #SNU, #HKUST, #NREL, #NCSU, #UNIMIB, #TUE, #WISC, #MIT, #UCSB, #NUEE, #MIE, #Google, #UNIPRESS, #ND, #EPFL, #FBH, #IEMN, #ONSEMI, #GATECH, #NYCU, #RCIQE, #SDU, #SINANO, #UTA, #UTAH, #GIST, #KUEE, #UCC, #ISE, #RIKEN, #KKLOS, #NEEL, #OVGU, #TYNDALL, #CST, #CRHEA, #INSP,

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Learn how Lam Research leverages virtual exploration to improve the yield for new device structures before performing costly wafer-based experimentation in this new blog post. https://bit.ly/4cmrpF1 . #LifeAtLam

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At advanced semiconductor nodes, traditional 2D design rule checking (DRC) often misses critical hot spots. Luckily the SEMulator3D® virtual fabrication platform presents a potential solution to better identify 3D failures, cut costs, and reduce reliance on wafer-based experiments. The Lam Research blog dives into the large area analysis process using SEMulator3D®. #LifeAtLam

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TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year 🤩 With N3E already in volume production, #TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of #FinFET #technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their #M4 #SoC, this is allowing them to reap the benefits of the improved process node relatively quickly. "N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at an event. "We have seen great yield performance on customers' products, so they did go to market as planned." TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density. Meanwhile, looking towards the immediate future at TSMC, N3P has finished qualification and its yield performance is close to N3E, according to the company. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/dkFujc2R #semiconductorindustry #semiconductors #technology #tech #innvoation #foundry #taiwan #chip #chips #icdesign #mobile #consumerelectronics #ai #datacenter #computing #computer #nvidia #amd #qualcomm #it #ml

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IS THE FUTURE OF MOORE’S LAW IN A PARTICLE ACCELERATOR? The system KEK is developing generates light by boosting electrons to relativistic speeds and then deviating their motion in a particular way. The process starts, Nakamura explains, when an electron gun injects a beam of electrons into a meters-long cryogenically cooled tube. Inside this tube, superconductors deliver radio-frequency (RF) signals that drive the electrons along faster and faster. The electrons then make a 180-degree turn and enter a structure called an undulator, a series of oppositely oriented magnets. (The KEK system currently has two.) The undulators force the speeding electrons to follow a sinusoidal path, and this motion causes the electrons to emit light. https://lnkd.in/dvyp9pAf

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Good article where Brian Bailey discusses some aspects of custom ASICs I am very interested in how developments in technologies such as advanced packaging and EDA tools may enable custom ASICs, as he outlines, I believe we are in a "wait and see" phase: - Will the 'beyond Moore' era of chip optimization instead of constant node shrinking lead to lower costs for specialized chips, specially in legacy nodes? - Will advanced packaging enable the combination of specialized legacy-node subsystems with advanced logic chiplets? At what cost point? - Will tool vendors be able to lower the complexity of customization and verification, making custom ASIC design available to a wider audience at lower costs? Those are some questions I believe people in the semiconductor industry should be paying attention to

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