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Questions are surfacing for all types of design, ranging from small microcontrollers to leading-edge chips, over whether domain-specific design will become ubiquitous, or whether it will fall into the historic pattern of customization first, followed by lower-cost, general-purpose components. Expedera Inc.'s Sharad Chole and Paul Karazuba comment in a recent Semiconductor Engineering article. https://ow.ly/fcCS50RJ2u6

Great article by Ann Mutschler from Semiconductor Engineering with incredible insights from several top global experts on how multi-die design is pushing complexity to the max from design and verification to packaging. “Everything was clock speed and performance in the good old days of IBM mainframes and Intel/AMD x86 servers,” observed Ashish Darbari, CEO of Axiomise. Thanks to the Arm architecture, from the late ’90s onward, power became the dominant push in the industry, and with chips being squeezed into smaller form factors such as mobile phones and watches and miniaturized sensors, performance along with power and area (PPA) determined the quotient of design complexity. 72% of ASICs are reported to manage power actively, and power management verification is a growing challenge, as reported by the Wilson Research report from 2022. However, with the rapid adoption of silicon in automotive and IoT, functional safety and security dominate the design complexity. You cannot design a chip without thinking of PPA — and one or both, safety and security. Test and verification have evolved from the days of architectural verification suites of the ’70s and ’80s to constrained random, formal verification, and emulation. Each of the new verification technologies copes with different abstraction levels of designs and, if used correctly, can be complementary. Whereas emulation can reason about functionality and performance at the full-chip level, constrained random and formal are great technologies at the RTL level, with formal being the only technology to build proofs of bug absence. We see an increase in the use of formal verification for architectural verification, as well as in finding deadlocks, livelocks and logic-related bugs.”  #3dic #multidie #semiconductors #eda #design #verification https://lnkd.in/g8B8Kb2v

key Segments of Semiconductor Ecosystem 1. Semiconductor Design: Companies: Companies in this segment focus on designing semiconductor components. They create the blueprint for the functionality and architecture of the chips. Examples: Intel, AMD, NVIDIA, Qualcomm, and Broadcom. 2. Semiconductor Fabrication (Fabs): Companies: Semiconductor fabrication involves the actual manufacturing of chips in specialized facilities known as fabs. These fabs are operated by companies specializing in semiconductor manufacturing. Examples: TSMC, Samsung Foundry, GlobalFoundries. 3. Electronic Design Automation (EDA): Companies: EDA companies provide tools and software used in the design and verification of semiconductor components, helping designers create and optimize their designs. Examples: Cadence Design Systems, Synopsys 4. Semiconductor Equipment Manufacturers: Companies: These companies produce the machinery and equipment required for semiconductor manufacturing, including lithography machines, wafer fabrication equipment, and testing tools. Examples: ASML (lithography machines), Applied Materials, Lam Research, KLA Corporation. 5. Semiconductor Test and Packaging: Companies: After the chips are manufactured, they undergo testing and packaging processes. Companies in this segment focus on testing and packaging solutions. Examples: Advantest, Teradyne, Amkor Technology, ASE Group. 6. Semiconductor IP (Intellectual Property): Companies: IP companies provide pre-designed and tested functional blocks (IP cores) that can be integrated into custom semiconductor designs, saving time and resources. Examples: ARM, Rambus, Imagination Technologies. 7. Distributors and Manufacturers' Representatives: Companies: These entities play a role in the distribution and sales of semiconductor components. They may act as intermediaries between manufacturers and end-users. Examples: Avnet, Arrow Electronics, Future Electronics. 8. Original Equipment Manufacturers (OEMs): Companies: OEMs integrate semiconductor components into their final products, such as smartphones, computers, cars, and consumer electronics. Examples: Apple, Dell, Samsung, General Motors. 9. End Users: Entities: These are the consumers and businesses that utilize electronic devices powered by semiconductor components. Examples: Individuals using smartphones, businesses employing servers and networking equipment, automotive manufacturers incorporating chips into vehicles. Source:TechoVedas

🥳 Intel Corporation Unveils Glass Substrates to cram 1 trillion transistors on a package by 2030.: Glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields. Glass substrates’ tolerance to higher temperatures also offers chip architects flexibility on how to set the design rules for power delivery and signal routing because it gives them the ability to seamlessly integrate optical interconnects, as well as embed inductors and capacitors into the glass at higher temperature processing. This allows for better power delivery solutions while achieving high-speed signaling that is needed at much lower power. These many benefits bring the industry closer to being able to scale 1 trillion transistors on a package by 2030. Glass substrates will initially be introduced into the market where they can be leveraged the most: applications and workloads requiring larger form factor packages (i.e., data centers, AI, graphics) and higher speed capabilities. #semiconductor #semiconductorindustry #tsmc #intel #samsung #imec #globalfoundries #smic #umc #innovation #ai #computerchips #machinelearning #broadcomm #transistor #cowos #skhynix #microntechnology #kioxia #nanya #toshiba #ymtc #yangtze #scaling #moore #manufacturing #production #fabrication #apple #nvidia #arm #amd #qualcomm #ibm #huawei #chip #chipdesign #chipmaker #memory #logic #cpu #processor #FEOL #BEOL #interconnects #dram #nand #3Dnand #nandflash #storage #asml #euv #lithography #pellicle #glass

 key Segments of Semiconductor Ecosystem 1. Semiconductor Design: Companies: Companies in this segment focus on designing semiconductor components. They create the blueprint for the functionality and architecture of the chips. Examples: Intel, AMD, NVIDIA, Qualcomm, and Broadcom. 2. Semiconductor Fabrication (Fabs): Companies: Semiconductor fabrication involves the actual manufacturing of chips in specialized facilities known as fabs. These fabs are operated by companies specializing in semiconductor manufacturing. Examples: TSMC, Samsung Foundry, GlobalFoundries. 3. Electronic Design Automation (EDA): Companies: EDA companies provide tools and software used in the design and verification of semiconductor components, helping designers create and optimize their designs. Examples: Cadence Design Systems, Synopsys 4. Semiconductor Equipment Manufacturers: Companies: These companies produce the machinery and equipment required for semiconductor manufacturing, including lithography machines, wafer fabrication equipment, and testing tools. Examples: ASML (lithography machines), Applied Materials, Lam Research, KLA Corporation. 5. Semiconductor Test and Packaging: Companies: After the chips are manufactured, they undergo testing and packaging processes. Companies in this segment focus on testing and packaging solutions. Examples: Advantest, Teradyne, Amkor Technology, ASE Group. 6. Semiconductor IP (Intellectual Property): Companies: IP companies provide pre-designed and tested functional blocks (IP cores) that can be integrated into custom semiconductor designs, saving time and resources. Examples: ARM, Rambus, Imagination Technologies. 7. Distributors and Manufacturers' Representatives: Companies: These entities play a role in the distribution and sales of semiconductor components. They may act as intermediaries between manufacturers and end-users. Examples: Avnet, Arrow Electronics, Future Electronics. 8. Original Equipment Manufacturers (OEMs): Companies: OEMs integrate semiconductor components into their final products, such as smartphones, computers, cars, and consumer electronics. Examples: Apple, Dell, Samsung, General Motors. 9. End Users: Entities: These are the consumers and businesses that utilize electronic devices powered by semiconductor components. Examples: Individuals using smartphones, businesses employing servers and networking equipment, automotive manufacturers incorporating chips into vehicles. For all semiconductor & AI related content, follow TechoVedas

Monolithic Dies vs. Chiplets As chiplets are the trend, it becomes important to think of scenarios where monolithic dies can be used. This is when I came across a research article published in ACM from DAC '22. It talks about quantitative cost models for chiplets. It very succinctly explains how costs are calculated for chips. The model helps in making decisions about whether a monolithic or multi-chip architecture is more beneficial. The industry is moving towards chiplets on a common substrate to achieve the reticle limit as Moore's law becomes harder to maintain. As the industry has designs ranging from monolithic dies to chiplets, depending upon the production quantities, the cost varies for the design being used. There are two types of costs involved in VLSI systems: RE (recurring engineering) and NRE (non-recurring engineering) costs. NRE refers to one-time costs like masks, software, and IP licensing. RE refers to fabrication costs like testing, wafers, and packaging. The NRE cost varies a lot, depending on the quantity being dealt with. With an increase in quantity, the NRE costs become minimal due to amortization. This model mainly deals with RE costs involved in the cost of raw chips, chip defects, raw packages, package defects, and known good dies (KGDs). NRE cost consists of the cost of designing chips, packages, and modules. It was validated based on AMD’s design. The model shows that multi-chip architecture is a growing trend and begins to pay off when we get closer to the Moore limit (advanced nodes). This also talked about how monolithic SoC is actually a better choice when the production quantities are not large enough to amortize the NRE costs of chiplets. Reference : Chiplet actuary | Proceedings of the 59th ACM/IEEE Design Automation Conference Image Source : https://lnkd.in/g7_6Z6xq

Several EDA companies have unveiled significant developments in partnership with Intel, including flows for Intel's embedded multi-die interconnect bridge (EMIB) assembly technology and 18A process. - Synopsys has introduced a multi-die reference flow and IP for Intel's EMIB, enabling the exploration and development of multi-die designs with a focus on signal, power, and thermal integrity. - Cadence's EMIB reference flow covers system-level planning, physical optimization, and analysis, extending to DRC-aware implementation and physical signoff. Cadence's full digital and custom/analog flows were certified for Intel 18A, accompanied by crucial IP offerings. - Siemens' Solido SPICE simulators received certification for Intel 16 and 18A nodes. Siemens also unveiled an EMIB reference flow incorporating thorough validation of EMIB silicon layouts. - Ansys enhanced its thermal management flow with the RedHawk-SC platform to support Intel 18A silicon manufacturing process. Additionally, Ansys joined the Intel Foundry Accelerator USMAG Alliance to provide secure design methodologies for U.S. security applications. These advancements highlight the strong collaboration between leading EDA companies and Intel, paving the way for innovative solutions in the semiconductor industry.

Design costs for a 7nm chip were around $249 million, whereas for a 2nm chip, they soared to approximately $725 million. This signifies a substantial threefold increase in design expenses when transitioning from a 7nm to a 2nm chip.

Intel's glass packaging technology is going to change how hardware architectures are envisioned and realized at a scale required for handling exponential growth in data generation and associated applications for realizing the value.  Intel expects glass substrates to enable ultra-large 24×24 cm SiPs housing multiple pieces of silicon. The new SiP's essentially look like Distributed Control Systems data processing node cards bridging the differences in systems packaging thereby IIOT hardware architecture may become standardized and unified. Glass offers a range of benefits over traditional organic substrates. Among its standout features is its ultra-low flatness for improved depth of focus for lithography, as well as superior dimensional stability for interconnects. This will be important for next-generation SiPs with even more chiplets compared to today's devices, like Intel's own Ponte Vecchio. Such substrates also provide superior thermal and mechanical stability, which allows them to endure higher temperatures, making them more resilient in data center applications.  #climatechange #iiot #hardwarearchitecture

🔌Optimizing Chip Design: The Crucial Role of PnR Flow in Modern Semiconductor Technology In the ever-evolving landscape of semiconductor technology, where smaller, faster, and more efficient microchips are the order of the day, it's essential to recognize the unsung hero behind these technological marvels: Place and Route (PnR) Flow. PnR Flow in a Nutshell At its core, PnR Flow encompasses two vital stages in chip design: 1. Placement: This phase is all about strategic decision-making. It determines the optimal physical locations of various chip components like transistors, logic gates, and memory cells. The goal? Minimize distances between components that frequently interact, all while considering critical factors such as signal integrity and power distribution. 2. Routing: Once the components are in place, routing takes center stage. It's the art of creating an intricate network of connections, often referred to as interconnects, between these components. These interconnects act as the information highways, facilitating the seamless flow of signals and data across the chip. Routing is an intricate puzzle that must be solved to minimize signal delays, reduce power consumption, and make efficient use of available chip space. Why PnR Flow Matters: 1. Enhanced Performance: A well-executed PnR Flow results in shorter signal paths, which translates to faster data transmission and a boost in overall chip speed and performance. 2. Efficient Power Use: In an era where energy efficiency is paramount, proper placement and routing play a vital role in minimizing power consumption. This contributes to the development of eco-friendly and sustainable chip designs. 3. Space Maximization: Space on a microchip is a precious commodity, especially as the demand for smaller and more compact chips rises. PnR Flow ensures that every square millimeter is used optimally. 4. Signal Reliability: Amid the complex network of interconnects, PnR Flow ensures signal integrity. It minimizes noise and interference, guaranteeing reliable data transmission. 5. Accelerated Innovation: In a fast-paced tech world, agility is key. A streamlined PnR Flow enables faster design iterations, reducing the time needed to bring a new chip to market. Challenges and Innovations: While PnR Flow is indispensable, it's not without its challenges: - Scaling Complexity: As chip designs become more intricate, PnR algorithms must handle increased complexity without sacrificing efficiency. - Heterogeneous Integration: Modern chips often incorporate various types of components, such as CPUs, GPUs, and memory, requiring intelligent placement and routing for seamless communication. - Multi-Patterning: Advanced manufacturing techniques sometimes necessitate multi-patterning, where a single layer is patterned multiple times. PnR algorithms must account for this to maintain precision. #SemiconductorTech #ChipDesign #PnRFlow #Innovation #TechInsights