Questions tagged [risc-v]
For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use.
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CH32V003 max GPIO current
I am trying to find what current can a GPIO of CH32V003 (the 10cent MCU) output. Its noticeably chinese english datasheet states (on p.21)
GPIO (General-Purpose Input/Output Port) can sink or output ...
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4
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1
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What does this mean in RISC-V opcode table
I want to check my understanding of how the imm[20|10:1|11|19:12] specifies the bit arrangements in the JAL (jump and link) instruction in RISC-V architecture?
I ...
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What is the injector pipeline stage in this RISC-V core?
The cores in the Efinix Sapphire SOC FPGA IP core have 6 pipeline stages (fetch, injector, decode, execute, memory and write back).
What is or might be the injector stage? I can't find it explained ...
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What Specific Optimizations Can ARM Implementations Do That x86 Ones Cannot (And Vice-Versa And Risc-V)
I believe this question is slightly different from others (ex: Why exactly does the x86 (primarily x86-64) instruction set consume more power than reduced instruction sets like arm?)
This question is ...
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Memcopy Instruction in Risc V
I designed a Risc V 32-bit single cycle processor without pipelining for a project. We are given to implement a new instruction called "Memcopy". It copies an array of size N from one ...
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RISC-V byte load and store
I have the confusion in the following RISC V programming statements. Can someone explain that why does the contents of s0 in the last comment shown. shouldn't it be 0x00000180 the same as we are not ...
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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Why do we shift by three in RISC-V loops?
In this youtube video, the instructor explained some basic code in RISC-V assembly, but i didn't understand why in the first line, he is shifting i by 3. Why do we have to multiply it by 8??
I feel ...
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Signal not Showing State Changes on Intergrated Logic Analyser (Vivado)
I have been using the Integrated Logic Analyser (ILA) on Vivado 2021.2 to log some signals from a RISC-V processor running on an FPGA (BASYS 3 FPGA development board).
The signals I am monitoring are ...
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Why using RISC-V over off-the-shelf chips is more energy efficient?
I am not an expert on the world of chips, but as a developer, I understand quite well how they work and what problem each chip solves.
I have been increasingly curious about RISC-V and, among other ...
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RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
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How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
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Generating Control Signals via Case statement vs Boolean function
I'm building a RISC-V processor recently, and I've encountered a question when constructing the control unit. That is, what's the difference between generating control signals through:
Case statement,...
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
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