Questions tagged [vivado]
FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.
314
questions
-1
votes
0
answers
8
views
How to list full path of all FDSE instances in Vivado design?
I want to see the path of all the FDSE instances in the Vivado design. Just to see where are these registers in the design, which .sv files. AS can be seen in first image that the in the utilization ...
0
votes
1
answer
51
views
Resource consumption of Ettus USRP devices [closed]
I am desiring to work with one of the Ettus USRP devices. I want to learn about resource and power consumption of each default image files?
Is there any way to open the RFNoC designs on Vivado with ...
- 19
0
votes
1
answer
70
views
How to use FPGA system clock for my design in vivado?
Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA.
I have ...
0
votes
0
answers
82
views
Simulating a noisy sine wave
I'm trying to simulate a sine wave with white Gaussian noise on my test bench. I have generated 40 values for this signal following @vipin's blog post here and integrated this module into my test ...
- 31
2
votes
1
answer
79
views
Divider Generator handshake is not working
I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
- 31
-1
votes
1
answer
108
views
Why does multiplication give 1 even though inputs are not 1? [closed]
When I'm doing multiplication inside an always block for my variables K_next_num and ...
-3
votes
1
answer
106
views
Whats the error?
I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct.
Someone can tell if I'm missing something, please.
- 39
0
votes
0
answers
131
views
Can't solve this Vivado synthesis problem - Any help?
I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
- 1,555
1
vote
3
answers
46
views
Increase operation width during the operation without extra registers in Verilog
I have two signals of type "reg" with different bit lengths:
reg [15:0] A;
reg [11:0] B;
I want to display the value of ...
1
vote
2
answers
48
views
Modeling Flip-Flops (RS, T, JK) in Verilog
I encountered an unusual behavior while simulating flip-flops in Verilog using Vivado.
Take, for instance, a four-bit up counter where I used an RS flip-flop for the most significant bit (...
- 283
0
votes
1
answer
24
views
Vivado and simulation for a 4-bit up counter
I am creating a 4-bit up counter using Verilog in Vivado.
For this counter, I would like to use flip-flops to represent each bits from Q0 to Q4.
For simplification, I used D flip flop to represent Q3, ...
- 283
0
votes
0
answers
52
views
How to remove or prevent automatically generated (* KEEP_HIERARCHY = "soft" *) in Vivado?
Now I'm debugging due to an unexpected working during simulation.
For example:
...
- 619
0
votes
0
answers
32
views
AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton
I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum.
While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
- 1
0
votes
1
answer
119
views
Xilinx Virtex-7 VC709 FPGA Clock Setup Problem
I am getting started with the Virtex VC709 FPGA board, moving on from a much simpler Digilent FPGA development board. I get critical warnings trying to configure a single ended 100MHz clock from the ...
- 1,555
2
votes
1
answer
69
views
D latch module in VHDL using NAND structure [closed]
What is the difference between a positive-level D latch and a negative-level D latch?
How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
- 133