Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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Brand new FPGA burnt?
So, when I plugged in my FPGA for the first time, it started to smell a bit like chemicals, and this showed up. Is it burnt, or is it just some type of residue that popped up once I connected it?
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Create ROM using Logic Elements vs Block RAM
In FPGAs, one can create a ROM using logic elements and also using block RAM. When using block RAM, we would follow the tool vendor's process to create a ROM.
For Quartus, this means that we specify ...
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How to list full path of all FDSE instances in Vivado design?
I want to see the path of all the FDSE instances in the Vivado design. Just to see where are these registers in the design, which .sv files. AS can be seen in first image that the in the utilization ...
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Hardware driver compiling from Vitis for USRP devices of Ettus
I am new at sdr world. I am willing to work on sdr from ettus (E320) I know about uhd and its usage from gnuradio. However I dont want to use any oot application on my computer and I am not sure about ...
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Latches Due to Asynchronous Load of a PISO Shift Register
What appears to be a simple problem raises a few questions regarding latches.
In trying to replicate a TI SN74HC165 PISO shift register within an iCE40UP FPGA, I've come up against a situation where a ...
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Feeding data stream to FPGA using PCIe [closed]
I am trying to use PCIe with ultrascale+ device and feed the fpga with data stream and send it to another device using PCIe over SFP+ optical cable. However, I don't know how to feed data to the fpga (...
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32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA
I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
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How AXI is implemented?
From what i understand AXI is interconnect standard, as far as i understand "interconnect" should be somthing like MUX allowing data pass from same port to different end-points.
Although i ...
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Weird FSM behavior on the start only
I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
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FPGA direct coaxial output is not working
I am using a Zynq device and trying to create a coaxial output port. To achieve this, I first connected the output of the I/O port to an LED and verified that it works correctly by inputting it into ...
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Lattice Diamond PLL Configuration for decimal output
I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
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Using register after multiplier in the MACC
I am creating a design that must be portable across different tools: Xilinx Vivado, Intel Quartus, Microsemi Libero. The design uses multiplier followed by adder that accumulates the results from the ...
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Resource consumption of Ettus USRP devices [closed]
I am desiring to work with one of the Ettus USRP devices. I want to learn about resource and power consumption of each default image files?
Is there any way to open the RFNoC designs on Vivado with ...
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Finding the largest std_logic_vector in an array (VHDL)
I am trying to create an output layer classifier for a neural network that is implemented on FPGA (in VHDL). The classifier should simply return the array index that contains the largest ...
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Yokogawa WT3000 don't boot
I have a Yokogawa WT3000 Power Analyzer which I was using with no problems and then I turned it off to take a break. An hour later, I tried to turn it on and I notice that it shows nothing on the ...
