Questions tagged [xilinx]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
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Stabilizing ODELAY_VALUE related to IODELAY2 module in Spartan6 SLX9 FPGA Design for SDRAM Interface
I'm working on an FPGA design for the Spartan6 SLX9, which includes a memory controller for off-chip Micron SDRAM. To introduce a delay on the clock signal to the SDRAM relative to the Data/Command ...
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How to use FPGA system clock for my design in vivado?
Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA.
I have ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Can't solve this Vivado synthesis problem - Any help?
I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
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How to remove or prevent automatically generated (* KEEP_HIERARCHY = "soft" *) in Vivado?
Now I'm debugging due to an unexpected working during simulation.
For example:
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AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton
I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum.
While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
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Virtex-7 FPGA Clock Constraint Configuration
I am moving from entry level FPGA such as Artix-7 (BASYS-3 board) to using a Virtex-7 (VC709 board). I have a question about how to setup the constraints file for the main clock of the Virtex-7 FPGA. ...
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Verilog: How do I assign multidimensional arrays as outputs in my module
I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way.
For Example:
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Simulating and verifying DDR3L clock
Context
I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?
I’m following a guide (Here is the link to the guide:
https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
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How to see the connections of each flip-flop in Vivado RTL schematic view?
I am trying to make the design shown below which is basically a shift register:
When I elaborate this design in Vivado, it shows me the following:
How can I see which flip-flops the inputs and ...
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How do I initialise an Unpacked array in Verilog?
I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:
reg [11:0] address[1:0];
For this, how do I ...
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Populating BRAM using a .coe file on Xilinx Alveo U280
I am new to the world of FPGAs.
I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
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Vivado Ethernet IP core licensing issue
I have a PL design in which I included a 10G/25G Ethernet Subsystem IP core from Xilinx configured with BASE-KR, AN/LT logic and FEC logic for Clause 74. When I try to generate the bitstream, I am ...
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?
I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...