J. Low Power Electron. Appl., Volume 14, Issue 2 (June 2024) – 16 articles
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In this paper, we present a low-power Injection-Locked Clock and Data Recovery (ILCDR) circuit using 28nm FDSOI technology. The back-gate auto-biasing of FDSOI transistors allows for a compact Quadrature Ring Oscillator (QRO) that is smaller and has reduced levels of power consumption compared to an LC tank oscillator. By injecting a digital signal, we achieve an Injection-Locked Oscillator (ILO) with a low jitter. This leads to a low power ILCDR with a fast locking time and low jitter for burst-mode applications. The key innovation is a complementary QRO using back-gate control with FDSOI technology, resulting in an efficient ILCDR circuit. Post-layout simulations show a recovered clock jitter of 26.7ps and a data jitter of 11.9ps with a power consumption of 318μW at 0.6V. The estimated chip area is around 6600 μm². View this paper
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