Acceler8 Talent

Physical Design Engineer

Acceler8 Talent Mountain View, CA
No longer accepting applications

Acceler8 Talent provided pay range

This range is provided by Acceler8 Talent. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$200,000.00/yr - $250,000.00/yr

Direct message the job poster from Acceler8 Talent

Acceler8 Talent has teamed up with a well-funded data center acceleration company seeking a Physical Design Engineer (STA) to report directly to the CEO.


This company is dedicated to creating a novel interconnect architecture to address congestion issues in extensively distributed systems. Their recent successful Series B funding round highlights their growth and potential.


The founding team has significant experience from leading hardware and technology firms, with primary investors who have a proven track record of guiding early-stage startups to success.


They are looking for a physical design engineer with extensive expertise in Static Timing Analysis on large, complex chips.


Responsibilities:


As a Physical Design/STA Engineer you will build and support the CAD tool flow for physical implementation in a cloud-first environment. You will handle physical implementation tasks from synthesis through tapeout and interface with foundry partners on IP and process technology. Strong experience with static timing analysis is essential.


Requirements:


  • Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes.


  • Expertise with Static Timing Analysis.


  • Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre.


  • Strong familiarity with various analysis tools such as Redhawk, Voltus. • Experience with circuit analysis using HSPICE is a plus.


  • Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages.


  • Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience. • Proven track record of execution on products which have shipped in high-volume


This fully position is open to candidates located in the San Francisco Bay Area, Austin, TX, Raleigh, NC, or Boston, MA.

  • Seniority level

    Mid-Senior level
  • Employment type

    Full-time
  • Job function

    Engineering
  • Industries

    Computer Hardware Manufacturing

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