Denis Place

Our latest blog on Power Spectral Density (PSD).

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Check out my new blog on using our #radhard #MCU to reconfigure #Space deployed #FPGA. Please reach out if you have interest and we can provide specific details on how to deploy

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Success Story – MEMS Microfluidics Wafer Probe System Applicationhttps://hubs.ly/Q02BkK0J0

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Tracking the Progress of the CHIPS R&D Programs Enacted in 2022 to promote U.S.-based semiconductor production and innovation, the CHIPS & Science Act is the most significant federal investment ever made in the U.S. semiconductor industry. While much attention is focused on the CHIPS incentives grant program, the other pillar of the CHIPS Act is also critically important: a substantial, $13 billion investment over 5 years in semiconductor research and development (R&D). The Department of Commerce is responsible for $11 billion, and the Department of Defense is responsible for $2 billion.  To assist the industry and other stakeholders in monitoring the progress of the CHIPS R&D Programs, SIA launched today a new resource tracking the progress of these initiatives. The CHIPS R&D programs include: CHIPS National Semiconductor Technology Center (NSTC) CHIPS National Advanced Packaging Manufacturing Program (NAPMP) CHIPS Metrology Program (Metrology) CHIPS Manufacturing USA Institute (MFG USA) DOD Microelectronics Commons (ME Commons) Thus far, the Department of Commerce has committed $5 billion to the NSTC, which will be operated by the National Center for the Advancement of Semiconductor Technology (Natcast) and $3 billion to the NAPMP. There is also an open funding opportunity for up to $285 million for MFG USA to establish the CHIPS Digital Twins Manufacturing USA Institute (SIA is supportive of an effort by the Semiconductor Research Corporation to lead this initiative). The CHIPS Metrology Program will be allocated approximately $519 million, and the program is currently supporting at least 30 ongoing research projects. Meanwhile, DOD has selected the 8 hubs that will serve as leaders of the ME Commons, committing $238 million of their total $2 billion. Intel Corporation: Received the largest grant of $8.5 billion, plus an additional $11 billion in government loans. Intel plans to invest $100 billion in new and expanded facilities across Arizona, Ohio, Oregon, and New Mexico. TSMC (Taiwan Semiconductor Manufacturing Company): Awarded $6.6 billion to construct a new chip plant with three fabs in Arizona. TSMC is expected to invest $65 billion in this project. Samsung Semiconductor: Received $6.4 billion in funding from the U.S. government. Micron Technology: Granted $6.1 billion to support its plans of investing $50 billion through 2030 for new fabs in Idaho and New York. GlobalFoundries: Awarded $1.5 billion in funding. Microchip Technology Inc. Technology: Received $162 million. BAE Systems: Granted $35 million, though this was not included in some visualizations due to the relatively small amount. #interesting #technews #technology #semiconductor #ai #innovation

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Join us for a collaborative webinar with Sierra Circuits on "Best Decoupling Capacitor Placement Strategies for PCB Designs"! July 24, 10AM PT Key Takeaways: 💡 Decoupling Capacitor Essentials: Importance and selection criteria (size, capacitance, ESR, ESL) for maintaining PCB signal and power integrity. 💡 Placement Techniques: Strategies for decoupling capacitor placement on PCBs with varying power plane configurations to ensure power integrity. 💡 Optimization and Simulation: Guidelines for optimizing trace and via routing and using simulation tools to design and validate decoupling networks. Don’t miss out! Register now and take your PCB design to the next level 👉 https://okt.to/2i4OFt #PCBDesign #Webinar #SierraCircuits #GetToKnowZuken

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Join us for a collaborative webinar with Sierra Circuits on "Best Decoupling Capacitor Placement Strategies for PCB Designs"! July 24, 10AM PT Key Takeaways: 💡 Decoupling Capacitor Essentials: Importance and selection criteria (size, capacitance, ESR, ESL) for maintaining PCB signal and power integrity. 💡 Placement Techniques: Strategies for decoupling capacitor placement on PCBs with varying power plane configurations to ensure power integrity. 💡 Optimization and Simulation: Guidelines for optimizing trace and via routing and using simulation tools to design and validate decoupling networks. Don’t miss out! Register now and take your PCB design to the next level 👉 https://okt.to/Vmyexa #PCBDesign #Webinar #SierraCircuits #GetToKnowZuken

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Our unique “live via ZOOM” training is geared for sales and marketing professionals from manufacturers, manufacturers’ reps and distribution…real world applications that the attendee can put into practice immediately…more to come…

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Join this upcoming AMD w ebinar on June 26th: Designing for Versal Adaptive SoCs with AI Engines using Simulink and Vitis Model Composer. This webinar will show an example design – targeting the programmable logic and AI Engines in a Versal AI Edge device, and features speakers from AMD, Avnet, and MathWorks. #TogetherWeAdvance #AdaptiveComputing #Webinar #Versal #Vitis

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Don’t miss the Chiplets: Building the Future of SoCs virtual event on July 24 & 25! We’ll explore technical trends, market demand, and new application areas around chiplets concepts, challenges, technologies, and more with @EE Times and @Embedded.com. Hear from Cadence experts on the role of EDA companies in the chiplet transformation and how you can get a jumpstart in designing your own chiplets. https://ow.ly/tPUE50SBWkM

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Join this upcoming @AMD webinar on June 26th: Designing for Versal Adaptive SoCs with AI Engines using Simulink and Vitis Model Composer. This webinar will show an example design – targeting the programmable logic and AI Engines in a Versal AI Edge device, and features speakers from AMD, Avnet, and MathWorks. https://lnkd.in/erkgRfwg   #TogetherWeAdvance #AdaptiveComputing #Webinar #Versal #Vitis

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Learn how to use the search panel in OrCAD X Presto to perform global searches, efficiently filter design elements, and accelerate your PCB design process with Shannon Henry: https://ow.ly/5L9650Req8q #orcad #orcadxpresto #searchpanel

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Efficiency is key to enable AI at the edge. In this video our VP of AI, Carlos Morales shows how efficiently and fast Ambiq Apollo5 (Cortex M55 on SPOT) can classify images. Reach out to hear more if you are curious! #edgeAI #CortexM55 #arm #efficiencymatters #subthreshold #SPOT #edgecompute #innovation #semiconductors

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 U.S. semiconductor manufacturing capacity is predicted to skyrocket by 203%! See below more info: The Semiconductor Industry Association (SIA) and the Boston Consulting Group (BCG) have released a report predicting a 203% growth in U.S. domestic semiconductor manufacturing capacity from 2022 to 2032, following the enactment of the CHIPS and Science Act. This is the largest projected increase globally. The U.S. is also expected to grow its share of advanced logic manufacturing to 28% of global capacity by 2032, up from 0% in 2022. The report suggests that the CHIPS incentives are set to revitalize U.S. semiconductor manufacturing and strengthen U.S. chip supply chains. It also highlights the need for policy actions to further strengthen supply chains, support R&D and chip design, grow the semiconductor workforce, and ensure maximum benefits from the CHIPS Act. The U.S. is projected to capture over one-quarter (28%) of total global capital expenditures from 2024-2032, ranking second only to Taiwan. Without the CHIPS Act, the U.S. would have captured only 9% of global capex by 2032. The report also emphasizes the importance of ensuring chip companies have open access to global customers and suppliers. It warns of potential supply chain risks due to non-market-based investments resulting from incentive programs and large-scale industrial policies. The report also notes the concerted efforts by governments and companies worldwide to increase resilience in the semiconductor industry. The U.S. CHIPS Act committed $39 billion in incentives for semiconductor manufacturing, and companies in the semiconductor ecosystem have announced more than 80 new projects across 25 U.S. states, totaling nearly $450 billion in private investments. These projects are expected to create more than 56,000 jobs in the semiconductor ecosystem and support hundreds of thousands of additional U.S. jobs. Despite these advancements, the report calls for additional government policy actions to address lingering supply chain vulnerabilities and to ensure America’s continued growth in the semiconductor industry. #interesting #technology #innovation #semiconductor ASML SK hynix Samsung Electronics Micron Technology SMIC Intel Corporation Lam Research TSMC

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Understanding thermal analysis is critical to more robust and reliable RF semiconductor system designs. In this article from Microwaves & RF, we’ll look at some of the key thermal-related issues design engineers should consider: https://ow.ly/SsPx50RpzaZ #QorvoRF

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📈⚡𝐄𝐥𝐞𝐯𝐚𝐭𝐢𝐧𝐠 𝐏𝐞𝐫𝐟𝐨𝐫𝐦𝐚𝐧𝐜𝐞 𝐰𝐢𝐭𝐡 𝐂𝐞𝐫𝐚𝐋𝐢𝐧𝐤 𝐛𝐲 𝐓𝐃𝐊 𝐄𝐥𝐞𝐜𝐭𝐫𝐨𝐧𝐢𝐜𝐬 In his most recent feature in Designing Electronics North America our very own Matt Reynolds delves into the powerful capabilities of PLZT (lead lanthanum zirconium titanate) capacitors, showcasing our cutting-edge CeraLink series. His article offers an insightful exploration of their role in high-performance applications and why these components are game changers for industries seeking the highest power efficiency and durability levels. 🚘 🔋 We've engineered our CeraLink capacitors to excel under the toughest conditions, ensuring high efficiency and reliability where it matters most. As Matt highlighted, these capacitors’ exceptional handling of high voltage and temperature makes them a game-changer in electronics design especially in the field of hybrid and #electricvehicles (xEVs). 👉 More information on CeraLink: https://lnkd.in/dKySWsss What opportunities do you see for enhancing your projects with the advanced capabilities of CeraLink capacitors? #TDK #CeraLink #Innovation #HighPerformance #EngineeringExcellence #FutureofMobility #emobility #xEV #EV

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Happy #CostModelMonday! I did a #fan-out panel-level versus wafer-level comparison at #IMAPS DPC this year, and I'm expanding on it for the IMAPS Symposium. I had a single #yield chart in my analysis previously, looking at yield crossover points in relation to how expensive the incoming chip was. I did a new analysis that looks at when the crossover point occurs for two different panel sizes. In this chart, the same package is built with fan-out packaging on a 300mm wafer and from two different panel sizes. The yield for the 300mm wafer example is held steady at 99%, while the yield is changed for the panel-level processes. For the package built with the 515x510mm panel, the crossover point occurs just past 95%. However, the crossover point is closer to 94% for the package from the 600x600mm panel. In other words, a little more yield loss can be sustained by the package from the larger panel before it no longer competes with a higher yielding package from the wafer.

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