John joined the University in September 2014 to take a part time role within the Advanced Processor Technologies Group in the School of Computer Science while maintaining his position as Director of Technology and System at ARM Ltd. Cambridge.

Joined ARM in February 2002, John took responsibility for their platform architecture products and roadmap. As Director of Technology and Systems he is now focused on various programs in pursuit of the company’s a long term capabilities and requirements across technology and associated systems. He maintains an active role in the research community and is involved in many projects across both hardware and software computer architectures. Having founded the technology and program in ARM for the development and market introduction of the ARM MPCore multicore technology, now adopted globally, he previously specialized in enterprise software with Microsoft in Redmond as Group Program Manager and product architect delivering the Exchange 2000 Conferencing Server.

With a role that spans across industry and academia, from nanotechnology, hardware design techniques and architecture, operating systems, software memory models, runtimes and language though to applications from embedded, enterprise and HPC, he able to cross the typical interface abstractions and realize novel and innovative solutions across a broad area of computer architecture.

Having defined and introduced the ARM multicore processors with its novel two level coherence and processor integration scheme, along with the subsequent big.LITTLE concept and software, John’s interests have moved on to how to scale such technology into the data-centre and high-performance applications in general.

With a keen eye on the commercial aspects for any exploitation, he has initiated and been involved in various EU funded consortium in the furthering of the ARM technology towards these goal. John was technical director of an FP7 headline project EUROSERVER that focused on research and innovation across the adoption of ARM technology through nanotechnology integration, a new software memory paradigm and heterogeneous runtimes, while maintaining extreme scalability and compatibility goals across various market segments, an approach that is now being used to deliver on the need for exascale level computation in projects funded by H2020 to over 40M euro.

In addition to the power efficient scalability aspect of rich multi-class heterogeneous hardware systems, he is also involved in projects around associated re-targetable and semantically aware software runtime and associated support in the advancement of compiler technology.

Currently he provide a research vision and technical leadership across a number of project from transistor level to exascale HPC system design. 

• Advanced Processor Technology

Since Prof. Goodacre has a part-time role at the University, he is unable to independently take students through to the completion of a PhD.  However, he is available for co-supervision of students wishing to cover topics that may otherwise overlap outside a single group in the school, or has a specific interest in the area of low power scalable computer architectures that span wider than a single domain of interest or across today’s recognised system abstractions, especially in the application and development of novel approaches to the realization the compute systems.

Currently Goodacre co-supervises two PhD students, one on the micro-architectural implications of silicon 3D design for general purpose processors, and another on the implications of system virtualisation in the design of high performance heterogeneous systems. He would welcome students that have found a primary supervisor to discuss their interest and his suitability in helping with their research.