Hans Jacobs

What are considered parasitic junctions in core analog layout, can be silicon saving junctions when it comes to ESD robustness. It’s often these hidden junctions that we don’t usually consider in day to day layout, that become the backbones of our ESD strategies. This is the sort of detail that we discuss during our ESD layout course; the next one of which, runs from Tuesday 21st May, through Friday 24th, delivered remotely. If you’re interested in participating or hearing more, please have your manager or HR department reach out to James Telfer for information on pricing and availability.

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Teledyne LeCroy PCIe 6.0 M616 Exerciser / Analyzer Demo - Flit mode traffic generation at 64.0 GT/s with PAM-4 signaling. https://lnkd.in/g_GBp-yp

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An almost exhaustive analysis on chiplet and 3D IC https://lnkd.in/ek8VHWDT

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total power will need to include power of digital layers also but PHY power is impressive

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SIM8202-M2 The SIM8202G-M2 is the Multi-Band 5G NR/LTE-FDD/LTETDD/HSPA+ module which supports R15 5G NSA/SA up to 2.4Gbps data transfer. It has strong extension capability with abundant interfaces including PCIe, USB3.1, GPIO etc. The module provides much flexibility and ease of integration forcustomer's applications. The SIM8202G-M2 adopts M.2 form factor, TYPE 3042-S3-B. AT commands of SIM8202G-M2 are compatible with SIM7912G/SIM8200X-M2 series modules. This also minimizes the investments of customers and enables a short time-to-market. It is designed for applications that need high throughput data communication in a variety of radio propagation conditions. Due to the unique combination of performance, security and flexibility, this module is ideally suited for many applications. #5g #wireless #iot #sim8202 #sim8202g #m2 #iotsolution #module #5gmodule #4g #modem #global #security #usb #technology

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I keep finding interesting ICs from our new ADI colleagues from Linear Technology and Maxim. One such IC which I had never seen before is LTC4415 which is around since 2012. It features two ideal diodes each capable of handing 4A with an on resistance of 50 milli ohm. If you have two power supplies, perhaps one is a battery, the EN1 and the inverted EN2 allow it to switch from one supply to the other once the voltage from supply 1 falls below a certain value. It also features resistor programmable current limits for both supplies and a thermal shutdown feature. The EN inputs can also be driven by a uC. Probably not designed with functional safety in mind but the functionality seems perfect for high availability functional safety systems. For the full datasheet see https://lnkd.in/epddrDCa #functionalsafetytom

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"Post Silicon Validation is a critical step in chip design, as it ensures that the intended behavior of the circuit is functioning properly and searches for any unexpected or erroneous behavior. Debugging is a significant part of this process, where errors must be isolated and localized. However, internal signals in the chip are not accessible from the external world or the debug designer, which is where Design for Debug (#D4D) insertion techniques come in. Two popular D4D methods include scan chains and trace buffers, which can be used along with crashlogs and direct pins. State-of-the-art methodology involves inserting D4D at higher levels of abstraction like register transfer logic, but earlier tools relied on doing this at the gate level. Scan-based debug technique is heavily used for #PSV debug and relies on reusing the DFT scan circuitry. The challenge is to stop the functional clock and enable the scan clock, shift out the pattern, and reproduce the same bug again and again, i.e. getting a deterministic pattern. Another issue is, scan dump always happens in response to an event, hence it may not capture whatever cased the event. If scan dump is not enough, then we can use trace buffers, which can dump the debug data before and after the event(using Embedded logic analyzer shown in the diagram). However, the limitation of the trace buffer is the depth, which results in silicon area penalty and is always a trade-off between depth and the number of signals that can be traced/trace time. Large muxes and programmable registers can be used to reduce the signals going into trace buffers.

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#USBHD2.0-A HOOD FOR USB 2.0 A CONNECTOR NOTES: 1. MATERIAL: PVC, LIGHT GRAY (PANTONE 400C) 2. ALL DIMENSIONS ARE FOR REFERENCE ONLY 3. COMPONENT SHALL BE INDIVIDUALLY PACKAGED IN ACCORDANCE WITH L-COM SPECIFICATION PS-0031.

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𝐃𝐢𝐠𝐢𝐭𝐚𝐥 𝐒𝐢𝐠𝐧𝐚𝐥 𝐏𝐫𝐨𝐜𝐞𝐬𝐬𝐢𝐧𝐠 (𝐃𝐒𝐏) 𝐅𝐥𝐨𝐰𝐬: 𝘈 𝘋𝘚𝘗 𝘧𝘭𝘰𝘸 𝘳𝘦𝘧𝘦𝘳𝘴 𝘵𝘰 𝘵𝘩𝘦 𝘴𝘦𝘲𝘶𝘦𝘯𝘤𝘦 𝘰𝘧 𝘴𝘵𝘦𝘱𝘴 𝘪𝘯𝘷𝘰𝘭𝘷𝘦𝘥 𝘪𝘯 𝘱𝘳𝘰𝘤𝘦𝘴𝘴𝘪𝘯𝘨 𝘢 𝘥𝘪𝘨𝘪𝘵𝘢𝘭 𝘴𝘪𝘨𝘯𝘢𝘭. 𝘏𝘦𝘳𝘦'𝘴 𝘢 𝘨𝘦𝘯𝘦𝘳𝘢𝘭 𝘰𝘷𝘦𝘳𝘷𝘪𝘦𝘸: 𝐒𝐢𝐠𝐧𝐚𝐥 𝐀𝐜𝐪𝐮𝐢𝐬𝐢𝐭𝐢𝐨𝐧: The first step involves capturing the analog signal from the real world using sensors or analog-to-digital converters (ADCs). This converts the continuous analog signal into a discrete digital representation. 𝐒𝐢𝐠𝐧𝐚𝐥 𝐅𝐢𝐥𝐭𝐞𝐫𝐢𝐧𝐠: The digital signal might need filtering to remove unwanted noise or extract specific frequency components. Different filters are used depending on the desired outcome. 𝐒𝐢𝐠𝐧𝐚𝐥 𝐏𝐫𝐨𝐜𝐞𝐬𝐬𝐢𝐧𝐠: This is the core stage where various mathematical operations are performed on the digital signal to achieve the desired outcome. This could involve tasks like amplification, modulation, demodulation, compression, or any other signal processing algorithm. 𝐒𝐢𝐠𝐧𝐚𝐥 𝐂𝐨𝐧𝐯𝐞𝐫𝐬𝐢����𝐧: If needed, the processed digital signal might be converted back into an analog signal using digital-to-analog converters (DACs) for further processing or transmission. 𝐎𝐮𝐭𝐩𝐮𝐭 𝐃𝐞𝐥𝐢𝐯𝐞𝐫𝐲: The final processed signal, whether digital or analog, is then delivered to the intended destination such as a speaker, display, or storage device.

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I get asked often for connectivity relevance for AI and LLM. Every single large language model today runs on compute clusters that are enabled by Marvell’s connectivity silicon. Read the Blog, to learn more, at: https://lnkd.in/g365SAyg #EssentialTechnologyDoneRight #Marvell

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Great OFC coverage by LightCounting. TeraSignal’s Intelligent Re-Driver in CMOS is changing the power, reliability and performance calculus between DSP and LPO modules.

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TSMC and Cadence are collaborating on next-generation #AI-driven flows, including the Cadence Cerebrus™ Intelligent Chip Explorer, for design productivity and optimization and Pegasus™ Verification System for Physical verification Signoff. #Cadence #Signoff #PhysicalVerification #Design #FoundryCertified “We have a distinguished track record collaborating with TSMC to deliver a broad set of innovations across EDA, packaging and IP to accelerate system and semiconductor design and enable customers to achieve aggressive time-to-market goals. These new certified design flows and standardized solutions allow customers to confidently design for TSMC advanced nodes and usher in improved design efficiency and technological advancements,” said Chin-Chi Teng, SVP and GM, R&D, Cadence. Read the press release here: https://ow.ly/bTym50REHjG

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DWM1001 module is based on the DW1000 ultra-wideband (UWB) transceiver #IC, which is an IEEE 802.15.4a UWB implementation. It integrates UWB (Ch 5) and Bluetooth #antenna, all #RF circuitry, Nordic Semiconductor #nRF52832 and a motion sensor. Key Features 1.Location accuracy to within 20 cm 2.UWB channel 5 printed PCB antenna (6.5 GHz) 3. 6.8 Mbps data rate IEEE 802.15.4a UWB compliant 4. 3-axis accelerometer motion sensor 5.Optimized for low power sleep mode: < 15 uA 6.Supply voltage: 2.8 to 3.6 V #dwm1001c #dwm1001 #module #uwb

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SystemVerilog is transforming RTL Design, gradually becoming the HDL for writing RTL and offering a more efficient and dynamic approach to hardware design. Explore the benefits of Enumeration type over parameters in Verilog, discover the versatility of Union Type, and witness how functions in hardware design are streamlining processes. Ready to dive in? Check out our course on using SystemVerilog for RTL Design at quicksilicon.in and step into the dynamic world of SystemVerilog! #QuickSilicon #HardwareDesign #vlsi #TechCourses #vlsifundamentals #VlsiDesign #VlsiCourses #SystemVerilog #RTLDesign #ElectronicsEngineering #ProcessorDesign

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Great article with insights by Bernard Murphy at SemiWiki.com, "Arteris Frames Network-On-Chip Topologies in the Car." "... while there is plenty of complexity in evolving car architectures and the consequent impact on subsystem chip/chiplet designs, connected on-chip through both coherent and non-coherent networks, the intent behind these systems is quite clear. We just need to start thinking about total car system architecture rather than individual chip functions." #Arteris #NetworkOnChip #Automotive https://bit.ly/3UiKqls

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