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For those who has experience with Intel x86 motherboard design and bring up. I'm in the middle of motherboard bring-up that has Intel Tiger Lake UP3 CPU.

Seems like I had a good run so far at power-up sequence. here is a list of all power rails \ signals that I already checked and validated that they are HIGH:

enter image description here as you see, I still can't get SLP_S5# = High, which means I'm still at the sleep state.

Note 1: power-up sequence is controlled by an FPGA.

Note 2: SLP_S0# is connected to 100K PU according to INTEL Platform Design Guide, as opposed to INTEL Validation board that has 100K pull down.I pulled SLP_S0# low from FPGA (now it’s on ~500mv voltage). This change Still didn’t get me to SLP_S5# = HIGH.

Note 3: I flashed BIOS Binary to BIOS-SPI FLASH AND seems like the SoC is trying to communicate with the SPI Flash but the SoC is not proceeding to higher states:

SPI_SI_FL (SPI_MOSI)

enter image description here

SPI_SO_FL (SPI_MISO)

enter image description here

SPI_CLK_FL (SPI_CLK)

enter image description here

SPI_CLK_FL (SPI_CLK) – R367 (ZOOM IN)

enter image description here

here is a schematic for my motherboard for those who have Dropbox account.

I would like to get some debug ideas that could help checking the source of the problem

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  • \$\begingroup\$ Did you try a SPI protocol analyzer to get SPI transactions decoded and see if any protocol/timing violations are there? Your clock waveform (at relatively slow 14MHz) does not look good. \$\endgroup\$
    – Ale..chenski
    Commented Feb 26 at 5:35

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