Note: As others have pointed out, absolute maximum ratings should never be intentionally approached.
They are the known failure point of the chip. However, they provide a
very useful design point for understanding how far away you are from
that maximum. This answer focuses on solving what's left of that
design problem -- namely, how far away should one be from that maximum
value (and why).
There are two big issues to consider when sizing output current in static situations: voltage output and thermal output.
Voltage output
As you increase the output current, the output voltage will begin to "fail" (be greater than expected for an output "low" and lower than expected for an output "high") due to the finite output impedance of the GPIO pin's output driver. This, in turn, will disturb the Q-point of your output-attached circuit.
This is especially interesting in the case of highly non-linear devices like LED's. If you change the voltage you apply to an LED a little bit, the current demand changes a lot more in relation.
This leads to the general principle that you want the output voltage to "error" by no more than 10% (to make your design life easier).
In order to go anywhere near the absolute maximums you will have to suffer something like >60% error in your output voltage. In fact, the specifications for your MCU don't even show you how much error there would be at that output level.
You'd get something like 1V out of an output "high" from a 3V VCC. That level isn't high enough to reliably signal "high" to other devices (in digital systems).
I extracted this figure from your datasheet link:
To design the current limit (here, given Vcc=3): 3 - 0.1(3) = 2.7
At 2.7V, the nominal current limit is 8mA -- that is, a bit less than your expectation of *30*mA or so... ;-)
Interesting note from device physics is that the n-side (low side) in almost every CMOS output driver I've looked at is a bit stronger than the p-type high side. This is because electrons (the majority carrier in n-type FET) move about twice as easily through the channel as holes (the majority carrier in p-type FET's). To compensate, chip makers double (approx) the size of the p-type transistor until the performance of the driver is roughly symmetrical, but the low-side usually retains a slight (<10% advantage) even so.
This case is no exception...
You can see in this figure that 0 + 0.1(3) = 0.3V --> 9mA, about 10% greater than the 8mA previously.
So you should install your LED's pointing into your chip if possible. That is, design them so that output low = LED illuminated. Something like this:
Thermal output
High currents in the pin driver = heat (obviously). Heat++ --> disaster. GPIO driver circuits are usually evenly distributed around the periphery of the die by geometric necessity (often times they determine the minimum size of the die).
In the case of this Atmel chip (ATMEGA8, see below), they most certainly are. The GPIO circuits are clustered around the dark blue wire-bonding sites in the cyan ring around the (dark) logic and memory areas in the center.
This is all just boundary estimation and slightly hand-wavy, but engineering is about getting things done, so here goes... ;-)
Using neighboring pins at high current levels should result in at least linear derating.
If you assume that the part distributes heat roughly evenly (fair assumption for your small die), you can get a first-order approximation by working backwards from the absolute maximum rating (40mA) and assuming that the neighboring pin will share 100% of the heat burden.
That means that if you have one 40mA (don't actually do this) output, its immediate neighbors should be at 0mA. 20mA output --> 10mA neighbors, etc...
If I've explained well enough, then it should now be clear that you pick the minimum between the two methods.
