Exciting Collaboration Update! 📣 Pegasus Physical Verification We have an excellent ongoing collaboration with Samsung Foundry, advancing #AI and 3D-IC semiconductor designs. Together, we're pushing the boundaries of technology to deliver innovative solutions for the industry's most demanding applications. Discover how Cadence and Samsung are accelerating chip innovation and helping businesses achieve first-pass silicon success. #DigitalDesign #PhysicalVerification #3DIC #Cadence #SamsungFoundry #Signoff Read the press release: ⤵️ https://ow.ly/ZqsZ50SjcCQ
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Founder & CEO at WhiteNoise Corporation | Tech Influencer | 31k Followers | 21 Million Impressions | DMs - Consulting & Partnerships
https://lnkd.in/dCjnASQN Chip Packaging Is the Next Battleground for Tech Lead, Cadence CEO Anirudh Devgan Says. > Cadence chief says US must invest in advanced 3D packaging. > Semiconductor tech has grown into matter of national security. #tsmc #samsung #intel #Semiconductorindustry #electronics #semiconductor #supplychain #manufacturingtechnology #processtechnology #engineering #manufacturing #technology #computerchips #business #innovation #semiconductors #chips #chipmaker #foundry credit: bloomberg
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A Meeting of AI Titans: Nvidia and TSMC CEOs Collaborate to Overcome Chip Supply Challenges #AI #AIchipsupplyconstraints #AIdevelopment #artificialintelligence #artificialintelligenceboom #CCWei #Electronics #geopoliticalrestrictions #globalAItrainingsystems #investorconfidence #JensenHuang #llm #machinelearning #mainlandChinavisit #MorrisChang #NvidiaCEO #Nvidiachips #Nvidiamarketvaluesurge #scalingAIcapacity #Semiconductorindustry #semiconductorindustrystockprices #stockrise #surgingdemand #Taipei #TSMCCEO #TSMCsupplychainpartners
https://multiplatform.ai/a-meeting-of-ai-titans-nvidia-and-tsmc-ceos-collaborate-to-overcome-chip-supply-challenges/?no_cache=1706284180
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TSMC: Ecosystem for 2nm #Chip Development Is Nearing Completion Speaking to partners as part of their annual Open Innovation Platform forum in Europe, a big portion of TSMC's roadshow was dedicated to the next generation of the company's #foundry #technology. TSMC's 2 nm-class N2, N2P, and N2X process technologies are set to introduce multiple innovations, including nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM) capacitor over the next few years. But in order to take advantage of these innovations, #TSMC warns, chip designers will need to use all-new electronic design automation (#EDA), simulation, and verification tools as well as #IP. And while making such a big shift is never an easy task, TSMC is bringing some good news to chip designers early-on: even with N2 still a couple of years out, many of the major EDA tools, verification tools, foundation IP, and even analog IP for N2 are already available for use. "For N2 we could be working with them two years in advance already because #nanosheet is different," said Dan Kochpatcharin, Head of Design Infrastructure Management at TSMC, at the OIP 2023 conference in Amsterdam. "[EDA] tools have to be ready, so what the OIP did is to work with them early. We have a huge #engineering team to work with the EDA partners, IP partners, [and other] partners." Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/d7FV6x9D #semiconductorindustry #semiconductors #semiconductor #chip #chips #ic #integratedcircuits #integratedcircuit #icdesign #foundries #taiwan #manufacturingtechnology #semiconductormanufacturing #ai #cpu #gpu #technology #tech #artificialintelligencetechnology #
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Want to learn about why 3DIC is so critical for the semiconductor industry? Check out this Bloomberg article by Jane Lanhee Lee and Debby Wu, featuring Cadence President and CEO, Dr. Anirudh Devgan, titled, "Chip Packaging Is the Next Battleground for Tech Lead, CEO Says." This article highlights 3DIC as a generative AI workload enabler and praises Cadence software as "...an indispensable design tool for semiconductor firms large and small."
Chip Packaging Is the Next Battleground for Tech Lead, CEO Says
bloomberg.com
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At the close of 2023, it's reported that #TSMC and #Samsung will delay the mass production of 4nm chips at their new fabs in the US from 2024 to 2025, posing a challenge to the Biden administration's #semiconductor expansion efforts. #Intel's move to commence 2nm production in 2024 has been hailed as a critical step, aligning with the US Chips and Science Act goals, including widening its semiconductor tech gap with #China through commercializing sub-2nm technology. https://lnkd.in/gN7DzTHc
ASML's High-NA EUV technology: Shaping the future of sub-2nm chips as US pushes ahead in semiconductor race
digitimes.com
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AI chip-makers pressed with aggressive time-to-market goals need the tools to help them get their chips into the hands of customers as quickly as possible. IC test and silicon bring-up are tasks that can affect both the quality and the time-to-market of AI chips. In this Semiconductor Engineering article, Lee Harrison, Director of Automotive Test Solutions at Siemens EDA, considers DFT and silicon bring-up, and how a tool solution should be able to do three things to speed up AI chip development time, including: Exploit AI chip regularity, Shift-left DFT and Eliminate DFT-to-test iterations Read the full article to learn more: https://sie.ag/FRvc8 #AIchips #DFTmarketleader #Tessent #designfortest #TessentStreamingScanNetwork #TessentSSN #semiconductor
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INTEL + SIEMENS = Energy-efficient CHIP manufacturing factory!! 👏👏👏👏 . . . . INTEL and SIEMENS had announced a 3 year long deal to improve INTEL's factory efficiently. The focus will be on energy efficiency and sustainability. INTEL is moving towards a NET 0 carbon footprint. That's the reason they are going for efficient natural resources. INTEL to compete with TSMC, they are undergoing a multibillion-dollar shift in its manufacturing operation i.e. cutting-edge CHIP tech EUV lithography. INTEL is the 1st company that is going to partner with SIEMENS to transform its manufacturing operation. Thoughts?? #semiconductors #intel #siemens #vlsi #chips #embeddedsystems
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Revolutionizing SEMICONDUCTOR industry | Transformed 10K Careers | Invited@IIT | Embedded | Startups | Public Speaker | LinkedIn growth
INTEL + SIEMENS = Energy-efficient CHIP manufacturing factory!! 👏👏👏👏 . . . . INTEL and SIEMENS had announced a 3 year long deal to improve INTEL's factory efficiently. The focus will be on energy efficiency and sustainability. INTEL is moving towards a NET 0 carbon footprint. That's the reason they are going for efficient natural resources. INTEL to compete with TSMC, they are undergoing a multibillion-dollar shift in its manufacturing operation i.e. cutting-edge CHIP tech EUV lithography. INTEL is the 1st company that is going to partner with SIEMENS to transform its manufacturing operation. Thoughts?? #semiconductors #intel #siemens #vlsi #chips #embeddedsystems
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Some cool details on advanced packaging including an in depth look at 4th Gen Xeon packaging! I love all the advanced technologies that have to come together to deliver this amazing product! #iamintel #xeon #advancedpackaging
Thank you to the CNET team for the fantastic coverage of our Advanced Packaging technologies. This is indeed a rare inside look into our Advanced Packaging fabs, where magic happens every single day. Home to thousands of engineers and technicians who are solving the toughest problems in semiconductor packaging and are making the impossible a reality,and inventing the future! #IAMintel https://lnkd.in/gPFwqmkZ
I Got an Early Look at Intel's Glass Packaging Tech for Faster Chips
cnet.com
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Earlier this year, I did a deep dive into chiplets, which are creating a buzz around the semiconductor industry, being hailed as the answer to addressing the computing performance needs of pervasive AI without having to have a produce a costly, single monolithic chip. Disaggregation is the key word. You can read that piece here. https://lnkd.in/eH-FNuD5 . In this piece, we raised quite a lot of challenges ahead. I'm pleased to say that we are going to be learning about and debating these issues and opportunities at the EE Times | Electronic Engineering Times and embedded.com 'Chiplets: Building the Future of SoCs' free virtual event. I'll be moderating this two-day event along with Sally Ward-Foxton. There's still time to check out the agenda and register here: https://lnkd.in/enKip33c . I'm looking forward to my panel today, which will look at the promise open chiplet ecosystems, if that's even possible. And today's agenda features keynotes from Shankar Krishnamoorthy of Synopsys Inc, Ramin Farjadrad of Eliyan Corporation, and Sujit Sharan of Intel Corporation. Plus today's agenda also includes talks from Alphawave Semi, Cadence Design Systems, Siemens EDA (Siemens Digital Industries Software), Synopsys Inc, Lam Research, Winbond, YorChip Inc, Celestial AI, Blue Cheetah Analog Design, Inc.. #chiplets #ai #semiconductors #chipdesign
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