TSMC and Cadence are collaborating on next-generation #AI-driven flows, including the Cadence Cerebrus™ Intelligent Chip Explorer, for design productivity and optimization and Pegasus™ Verification System for Physical verification Signoff. #Cadence #Signoff #PhysicalVerification #Design #FoundryCertified “We have a distinguished track record collaborating with TSMC to deliver a broad set of innovations across EDA, packaging and IP to accelerate system and semiconductor design and enable customers to achieve aggressive time-to-market goals. These new certified design flows and standardized solutions allow customers to confidently design for TSMC advanced nodes and usher in improved design efficiency and technological advancements,” said Chin-Chi Teng, SVP and GM, R&D, Cadence. Read the press release here: https://ow.ly/bTym50REHjG
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Cadence Design Systems: AI R&D Upside Risk Summary Cadence Design Systems is a key player in the semiconductor sector, providing Electronic Design Automation (EDA) for chip designers. The company has outperformed its competitors over the past decade and has a premium valuation due to its steady growth and high margins. There is potential for further growth in the future, driven by increased demand for EDA in the race for AI capabilities in the semiconductor industry. Maintaining a PEG of 2.5x the YE25 price target may rise to $434 (+40%) on current consensus estimates. High margins and cash flow provide for share buybacks at 2x stock compensation cost. https://lnkd.in/eZrFfHHW
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Samsung Foundry has announced that it's working on the SF2 GAAFET process to outdo its main rival in a future 2nm node category. The company's advanced process technology has already earned it an order to produce a 2nm AI accelerator from Japan's largest AI company, Preferred Networks. Additionally, Qualcomm, the world's largest system semiconductor design firm, is in discussion with Samsung Electronics' System LSI Division to produce 2nm prototypes. #samsung #techgiants #chips #chipmaker #foundries #chipdesign #advancedtechnology #semiconductors #semiconductor #semiconductorindustry #semiconductormanufacturing #innovation #technology #technologynews
Samsung Foundry Showcases Advanced Technology and Solutions | Samsung Semiconductor Global
semiconductor.samsung.com
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Intel and Cadence push boundaries in 3D-IC, EDA flows, and semiconductor IP for Intel 18A, driving AI innovation and advanced system-level design capabilities forward. Intel Corporation Cadence Design Systems #3DIC #EDAsolutions #semiconductorIP #Intel18A #AIinnovations #systemleveldesign #advancedpackaging
Intel Collaborates with Cadence on Systems Foundry Enablement
https://electronicsclap.com
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TSMC SAYS IT DOESN'T NEED HIGH-NA EUV CHIPMAKING TOOLS FOR 1.6NM-CLASS NODE, BUT INTEL HAS CHAMPIONED THE TECH Article Summary: 1. #TSMC unveils A16 process technology with Super Power Rail backside power delivery at North America Technology Symposium 2024. 2. Unlike #Intel's approach, TSMC's A16 doesn't rely on High-NA EUV lithography, leveraging innovative techniques for cost-efficient production. 3. TSMC balances technological advancement with cost-effectiveness, exploring High-NA EUV lithography for future process technologies while optimizing existing tools for improved performance and yield. Thanks again to Tom's Hardware for the full article with more background and insights click the source link in the comments below 💡 🙏👇 Do you value meeting face-to-face with top executive leadership and decision-makers in the semiconductor industry? Experience the power of 1-on-1 business discussions at the International Semiconductor Executive Summits (ISES) events! Witness firsthand industry roadmap discussions and come experience firsthand the millions of dollars in future business collaborations that take place at this extraordinary gathering. Feel free to contact me for more details. #artificialintelligence #usa #nandflash #memory #chip
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In a recent announcement at the TSMC 2023 OIP Ecosystem Forum, TSMC introduced some significant advancements that promise to shape the future of semiconductor design and technology. Here's a summary: 1. TSMC has introduced 3Dblox 2.0, a groundbreaking open standard designed to enhance 3D IC design. This innovation holds the potential to make chip design significantly more efficient and powerful. 2. A open Innovation Platform's 3DFabric Alliance is expanding and strengthening its collaboration with industry leaders. This alliance is focused on integrating various critical components, including memory, substrate technology, testing, manufacturing, and packaging. 3. The forefront of pushing the boundaries of 3D IC innovation. The company is committed to making advanced silicon stacking and packaging accessible to a wider customer base. Dr. L.C. Lu, TSMC Fellow and VP of Design and Technology Platform, highlighted the growing need for industry-wide collaboration, particularly in the context of the next-generation artificial intelligence, high-performance computing, and mobile applications. Industry giant AMD has also recognized the significance of this collaboration. Mark Fuselier, SVP of Technology and Product Engineering at AMD, praised TSMC's contribution to their next-gen MI300 accelerators. This open standard, introduced last year, introduces an innovative approach to 3D IC design. It focuses on early design capabilities for power and thermal feasibility studies, with support for chiplet design reuse, ultimately enhancing design productivity. TSMC has established the 3Dblox Committee, an independent standard group, to ensure seamless system design with chiplets from various vendors. Collaboration with leading EDA partners is aimed at creating a comprehensive industry-wide specification. Collaborative efforts encompass: - Memory: Enhancing SRAM and DRAM memory bandwidth. - Substrate: Streamlining substrate design with a Substrate Design Tech file. - Testing: Addressing 3D test challenges for better chiplet testing. #TSMC #Semiconductor #Innovation #3Dblox #3DIC #Technology #Collaboration #AI #HPC #Mobile
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🔥 ASML, the sole global manufacturer of advanced EUV equipment, is reportedly set to manufacture ten equipment capable of producing 2nm chips next year. 🌐 With major semiconductor foundries, including #Samsung, #Intel and #TSMC, eyeing on producing 2nm chips by 2025, the competition to secure key equipment for utilizing the 2nm process is intensifying. 💡 Dive into details about the current 2nm race and the leader now : https://buff.ly/48bA4sk #2nm #ASML
[News] The Battle on Advanced Processes Intensifies as ASML Plans to Produce Ten Equipment Capable of 2nm Chip Production Next Year | TrendForce Insights
https://www.trendforce.com/news
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https://lnkd.in/gcbJ3zYX Meta's Next-Gen AI Chip: RISC-V Core, 2026 Launch. > This forthcoming chip is slated to integrate Andes Technology's RISC-V core and leverage TSMC's 5nm fabrication process, with an anticipated completion of development by 2025 and an official launch in 2026. #meta #artificialintelligence #riscv #Semiconductorindustry #electronics #semiconductor #supplychain #manufacturingtechnology #processtechnology #engineering #manufacturing #technology #computerchips #business #innovation #semiconductors #chips #chipmaker #foundry credit: smbom
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We've been hearing a lot from Intel Corporation in the past few weeks as rolled out its Foundry Direct Connect as "the first systems foundry for the #AI era." The get-together laid out some additional plans for Intel’s foundry effort. Intel has a full array of IP and EDA vendors, including our member companies Siemens EDA (Siemens Digital Industries Software) and Cadence Design Systems. In his latest blog post, Dean Freeman shares what the industry pundits are saying about this latest Foundry effort: Will it flounder like previous attempts? Or will it prevail? https://lnkd.in/gEt5vFk5
Will the Intel Foundry Model Succeed? - 3D InCites
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I am excited to share that Intel has joined the #3Dblox Committee to co-develop neutral 3DIC advanced packaging design formats. This allows us to expand our longstanding collaboration with #TSMC and #EDA suppliers on the important topic of interoperability and standards development. Intel brings its deep expertise with #3DIC advanced packaging enablement to this alliance, focused on implementing robust and interoperable design flows in a new era of disaggregated products. EDA suppliers can leverage 3Dblox formats and drive seamless design flows from 3DIC design cockpits. Intel’s Lalitha Immaneni, Vice President of Architecture, Design, and Technology Solutions, emphasizes, “Interoperable EDA formats for 3DIC are crucial to achieve maximum flexibility and design productivity. Together with 3Dblox committee members (Ansys, Cadence, Siemens, Synopsys, TSMC) we can enable a broad ecosystem to help design companies to quickly implement their disaggregated strategies.” It is significant that the two largest 3DIC semiconductor manufacturers in the world are part of 3Dblox. Welcoming Intel, Dr. L.C. Lu from TSMC said: “3D silicon stacking, and advanced packaging technologies are set to transform the semiconductor industry by enabling designers to achieve unprecedented levels of performance and power efficiency. The 3Dblox standard fosters an open ecosystem to harness the full potential of 3DIC designs with qualified design solutions, and we are thrilled to see Intel joining forces to continue evolving 3Dblox technology to address future market demands.” #Ansys #Cadence #Siemens #Synopsys #TSMC
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