Ram V.’s Post

Can you defy the diminishing returns of Moore’s law? In the recent past, every successive advanced process node (16nm => 7nm => 5nm) is resulting in lesser benefits with increasing cost per transistor. But, the need for compute and network capacity is only going up. Against this backdrop, our team has been doubling the performance of our Switching and Routing chips every 18-24 months, predictably. BTW, every time you double the performance of a Switch / Router chip, you replace 6 of the previous generation chips thereby resulting in 75%+ reduction in power, latency, and cost. To achieve this, we keep innovating to make things possible beyond what is supported by process node improvements. Our Tomahawk5 announcement today is another example of our relentless innovation and execution. Many thanks to our team, partners, and customers for helping make this happen!🙏 https://lnkd.in/etixQJAu

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Tim Mazumdar

FPGA Engineer at Major defense contractor

1y

As much as I appreciate the release of the 5nm 51.2 Tbps chip let me brutally go through your comments . I congratulate BRCM R & D & I comment on the piece.. 5nm is just CMOS - its allows the forwarding engines and the actual fabric to run a a very high clock rate due to lower capacitance and lowered Vdd and essentially utilizes the Chandrakasan -Brodersen equation. P = C*Vdd^2*f + Pleakage - contributory terms C is lower at 5nm compared to 7nm , Vdd drops and f increases (2X). The factors that make a Switching chip successful you emphasized NONE of them. 1. It is well known via NS3 simulations that a shared massive packet buffer in TMHWK IV allows the accomodate of elephant flows coexisting with "runt" flows. Allows runt flows not to get sidelined in the output packet buffer. There is a series of results on this by Andy Bechtolsheim and am sure from BRCM R & D. The shared output buffer also ensures that the "Elephant flow" does not have spend a lot of time in the buffer. Its a sub optimal balance that depends highly on the Mix of Flows. If there is leftover space on the output buffer ( 1 - alpha)* Buffer capacity - the algorithms depend on the remaining buffer space.

Tim Mazumdar

FPGA Engineer at Major defense contractor

1y

The greatest single reason by BRCM and Marvell and INTC continue to build these engines is a simple mathematical upper bound equation. Something that was derived by taking a derivative and setting the dT/dk to zero. Delay comprises of two terms - the number of nodes in the network, the BW of the Network and the switch radix. bigger the Radix a number of K= 16 to 32 increases the Number of Nodes exponentially. In this equation N is the number of nodes in the network. k is the radix of the switch , B is the bandwidth of the router distributed over 2k ports . L is the packet length (Byte) and "tr" is the router delay. Number of hops is reduced as k increases it is 2logk(N). As k doubles the number of hops drops exponentially. Lowered number of hops for a given very large N is the major way to drop Data center power.

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Martin Lund

Executive Vice President @ Cisco | Common Hardware Group

1y

Congratulations to the entire Broadcom switching team on 20+ years of relentless execution and continued silicon integration and innovation #XGS #DNX

Congrats Ram V. and Tomahawk5 team! Impressive! To appreciate this chip’s capacity - let’s step back and humor a quick real-world comparison - the world population is say, 8 billion people, and they are all watching 4K video. = 8 billion X 12 .5 mbps (for ease of math) = 100,000 tbps. So, total addressable market for Tamahawk5s would be a whopping 2000 chips. :) well, of course, modern workloads inside the data-centers, i.e. the east-west traffic makes north-south traffic look like a rounding error.

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Juan Lage

Technology Strategist | Mobility and Transportation | Data & AI Geek | Public Speaker

1y

Indeed, truly impressive!

Gary Middleton

Vice President Networking at NTT DATA, Inc.

1y

Congratulations Ram and team. Looks like a great step forward in performance and helping organzations improve the sustainability posture of their networks. Nice!

At device level it is true the advanced process technology offers better PPA. But this kind of break though can only be possible from an efficient pipeline structure, scalable architecture and ML algorithms. Congrats!!

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Yuval Bachar

Founder & CEO at ECL - Innovating and building the first Hydrogen based fully sustainable data center with 8 months delivery time

1y

Ram V., this is fantastic news. Congratulation, and keep up the innovation cycle to deliver the networking future.

Awais Nemat

Founder & CEO at Chkk

1y

Congratulations Ram!

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