Kelly Oppliger’s Post

PCIe and Chiplet design and related standards are a hot topic these days. Passing along this webinar info from the pros at Keysight Technologies. Always learn a lot from them, so passing this along!

Signal Integrity Toolbox includes Compliance Kits for various industry standards, supporting those designing SerDes and systems (both pre- and post-layout!) that adhere to these benchmarks. These kits are designed to streamline the validation process, reduce time to market, and ensure reliability in high-speed communication systems. Key Benefits: - Comprehensive coverage for 50 industry standards, like PCIe, Ethernet, USB, DDR, and more. - Accelerate the development and validation of SerDes or system designs. Drop in what you want to test and hit simulate! - Validate designs against eye masks and other performance to ensure reliability. These kits are a great resource for engineers and designers looking to meet the requirements of today's industry standards. Explore the examples to see how they can facilitate your design process. Learn more about how the Signal Integrity Toolbox can support your designs: https://lnkd.in/etNkK_KW

TIF On Demand: As technology advances and data transfer demands increase, it is critical to understand the latest best practices for PCI Express 6.0 electrical design and validation. Hear experts from Tektronix, Synopsys, and Anritsu as they discuss key considerations to design for the future of high-speed interconnect, from understanding the latest technology timelines to leveraging advanced simulation and testing methodologies. Sign up here: https://bit.ly/3O5M2vg to learn about the future of PCIe, 64 GT/s and beyond. #Tektronix #PCIE #EngineeringTheFuture

We are gettin' really really close to putting the new Matrix Portal S3 https://lnkd.in/eEy-XRjx into the shop, here's a tester we use to burn in the self-test code. The RP2040 brains https://lnkd.in/eGCQmvnt resets the S3 into the ROM bootloader, the sends over compressed binaries via USB. when the self-test starts up it notices that it's in the test jig and performs a self test of the GPIO and voltages. once done, it turns into a demo board that has a basic matrix display output for users to verify functionality. This way we only have to program the board once! Espressif Systems #adafruit #electronics #Espressif #opensource #opensourcehardware #MatrixPortalS3 #Innovation #TechDevelopment #CircuitTesting #RP2040 #NextGenTech

High speed IO(HSIO) like PCIe when used in the backplane type of applications go through several challenges. High speed signals have to traverse through following. [1] On Chip traces [2] Packages [3] Package vias [4] Backplane connectors [5] Backplane trace [6] Backplane via [7] Line card via [8] Line card traces Item 1,2 and 3 repeat for two communicating Silicon. During this journey they take brutal hit with: [1] Cross talk [2] Reflections [3] Channel loss [4] Channel discontinuities On the top imagine effects of PVT variations for silicon, PCB material issues, connector issues, trace variations, material variations, vendor variations. Yet it works. Pushing to 64 GT/s at Gen 6. Its beyond my imagination. #PCIe #HSIO

iMX DevBoard design. Day 7. Hi! What is done since previous step: 1) DDR4 IC is selected. MT40A512M16LY-062E:E (Micron) chip will be used. The criterias of selection are the same with the wireless interfaces module selection: full documentation, popular brand, 512Mb x 16 configuration. 2) EMMC64G-TY29-5B111 (Kingston) is used as eMMC IC. eMMC is required to storage files (for example, media files) when power is off. 3) IS25WP064A-RHLE-TR (ISSI, Integrated Silicon Solution Inc) is NOR flash IC is not so fast in comparison with NAND, but it is more reliable. That is why NOR will be used to storage software/firmware and cinfigurations files for LTE, BLE, etc. 4) It is not always convenient to use MIPI-CSI/DSI interfaces and sometimes you will need USB for camera and HDMI for displays. Thus I decided to provide an opportunity to use as MIPI, as HDMI and USB to connect display and camera. 4.1) EZ-USB™ CX3 (Infenion) MIPI CSI-2 to SuperSpeed USB bridge controller is for camera. I decided to place it as an additional option, becouse price of this IC is around 15$-25$ for piece (depends on bulk).What is good with CX3 is big database for developers. Documentation is full, undertandable, there are a lot of examples presented, so mistake probability is minimum. 4.2) ADV7533 (Analog Devices) is for MIPI-DSI to HDMI conversion. This is very popular and interesting IC, so why not. The next step around MIPI and Memory interfaces is to think over schematic. #electronics #nxp #DDR4 #DDR #EMMC #NOR #IMX8M #hardware #MIPICSI #MIPI #MIPIDSI #Video #Memory #Infenion #Micron #Kingston #ISSI #AnalogDevices

Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7 - Part 2 In the previous article, we delved into the fundamental architecture of the PCIe Card Electromechanical (CEM) connector, exploring the nuances in Signal Integrity (SI) performance criteria between PCIe Gen6 and Gen7. We focused on both connector-only performance and overall channel performance, emphasizing additional design considerations for Add-In Cards (AIC) and baseboard/motherboard to push the insertion loss drop off frequency, alongside simulation parameters and material choices for the housing of the connector. In this article, we pivot to showcase a marked improvement in SI performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design. https://lnkd.in/gxhH_EpR

Craving space-saving solutions? Look no further! Elevate your designs for space-constrained applications with the extraordinary #Molex Micro-Fit+ PCIe 5.0 connectors. Witness the perfect blend of high current capacity and unparalleled compact efficiency. But wait, there's more! Engineers, envision the possibilities when the mating force is reduced by a staggering 40%. Brace yourself for a revolutionary assembly process. 🚀 Immerse yourself in the future of connector technology and unlock the potential to transform your space-limited applications. Explore the realm of 👉https://lnkd.in/gmSFU2Sy. For more in-depth information or questions, my DMs are open! #EngineeringInnovation #SpaceOptimization #Connectivity #Efficiency #Molex

TMS320F28335PGFA • High-performance static CMOS technology – Up to 150 MHz (6.67-ns cycle time) – 1.9-V/1.8-V core, 3.3-V I/O design • High-performance 32-bit CPU (TMS320C28x) – IEEE 754 single-precision Floating-Point Unit (FPU) (F2833x only) – 16 × 16 and 32 × 32 MAC operations – 16 × 16 dual MAC – Harvard bus architecture – Fast interrupt response and processing – Unified memory programming model – Code-efficient (in C/C++ and Assembly) • Six-channel DMA controller (for ADC, McBSP, ePWM, XINTF, and SARAM) • 16-bit or 32-bit External Interface (XINTF) – More than 2M × 16 address reach • On-chip memory – F28335, F28333, F28235: 256K × 16 flash, 34K × 16 SARAM – F28334, F28234: 128K × 16 flash, 34K × 16 SARAM – F28332, F28232: 64K × 16 flash, 26K × 16 SARAM – 1K × 16 OTP ROM • Boot ROM (8K × 16) – With software boot modes (through SCI, SPI, CAN, I2C, McBSP, XINTF, and parallel I/O) – Standard math tables • Clock and system control – On-chip oscillator – Watchdog timer module • GPIO0 to GPIO63 pins can be connected to one of the eight external core interrupts • Peripheral Interrupt Expansion (PIE) block that supports all 58 peripheral interrupts #electronic  #electronics  #electroniccomponents  #interesting  #knowledge

As technology advances and data transfer demands increase, it's critical to understand the latest best practices for PCI Express 6.0 electrical design and validation. In this TIF on-demand webinar, our experts from Tektronix, Synopsys, and Anritsu discuss key considerations to design for the future of high-speed interconnect, from understanding the latest technology timelines to leveraging advanced simulation and testing methodologies. Get invaluable knowledge to navigate the future of PCIe with 64 GT/s and beyond. Watch Now: https://lnkd.in/gZHPf564