Progress at DZK Labs: The Journey of 'Thumbelina'
We are pleased to share an exciting update from DZK! As part of our ongoing development, we have joined the Efabless Corporation's shuttle program to tape out a silicon-proven prototype called 'Thumbelina'. This project represents a significant step in our journey, showcasing area-efficient BLS12-377 units for Zero-Knowledge Proofs (ZKP) with a special emphasis on Aleo Mining.
At the core of 'Thumbelina' is a modular multiplication unit that remarkably claims just 0.6 mm² in a 130nm process. However, 'Thumbelina' is not just a codename for a silicon-proven prototype. When viewed through #Klayout, our design forms the shape of a girl holding flowers. Additionally, the eFabless chip's size of only 10 mm² makes it smaller than a baby's thumb!
This journey has been inspired by the recent prominence of FPGA in accelerating ZKP. It has been energizing to see events like the ZPrize, sponsored by Aleo, Jump Crypto, and Polygon Labs, fueling technological advances and pushing the boundaries of what we once thought was possible.
Nevertheless, we're aware of a potential pitfall in FPGA technology – overoptimization. Features specific to FPGA, like DSP, often don't translate well to Application-Specific Integrated Circuits (ASIC), leading to significant reworking of low-level building blocks during the transition. At DZK, we're addressing this challenge head-on, adopting a platform-agnostic approach to ensure smooth transitions and future-proofed designs.
Our 'Thumbelina' chip is expected to return from the foundry in October. We understand that this initial iteration still leaves plenty of room for future improvements. Therefore, we are looking forward to the opportunities this journey offers us to learn and grow.
Stay tuned for more updates on our progress and the insights we glean from this journey. Your support fuels our innovation, and we can't wait to see where this path will lead us next.
#ZKP #ASIC #ZPrize
