Anusha Dixith G’s Post

Delve into one of our highlighted papers from April 2024, titled "ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption". Authored by: Xiao Hu; Zhihao Li; Zhongfeng Wang; Xianhui Lu 📝 Volume: 32, Issue: 4, April 2024 The homomorphic encryption over the torus (TFHE) is a promising fully homomorphic encryption (FHE) scheme that allows arbitrary homomorphic computations with the programmable bootstrapping (PBS) algorithm. However, PBS suffers from prohibitive computation complexity and latency, which hinders the practical applications of TFHE. To address these challenges, we propose ALT, a field-programmable gate array (FPGA) accelerator for PBS that exhibits high area efficiency and low latency. Continue reading on IEEE Xplore: https://loom.ly/OmkKmWI #IEEE #EditorialBoard #TVLSI #VeryLargeScaleIntegrationSystems #VeryLargeScaleIntegration #PaperHighlight

Thrilled to share with you that recently, my fellow mates Prajwal Kodihalli, shreyas wandkar, and I, under the guidance of Basawaraj Sir, have presented three research papers at the 8th International Conference on Information and Communication Technology for Intelligent Systems (ICTIS 2024), titled as follows: 1] Multi-object segmentation and tracking system on Zynq UltraScale+ MPSoC 2] Object tracking system on Zynq UltraScale+ MPSoC 3] Real Time Multi-Object Detection and Tracking on Zynq UltraScale+ MPSoc ZCU104 Each of these papers explores a different application of AMD's Xilinx Zynq UltraScale+ MPSoC ZCU104 board using various algorithms. These works pave the way to develop efficient and reliable computer vision solutions on the computer embedded systems. #conference #computervision #researchpaper #embeddedsystems

On Dec 6-2023, there is another event of the series: "FIRE: FPGA Innovation Research Exchange" organized by SURF, together with the HW Acceleration Network community. This time it's a HW acceleration workshop focused on application development using a HW-SW co-design approach. The focus of this event is on optimizing applications on heterogeneous CPU-accelerator systems, addressing system design challenges to achieve full system optimization. We invite speakers from industry and academia to share their thoughts and experiences in using GPU and FPGA accelerated systems for a number of relevant applications domains. 👉 Registrate (free) https://buff.ly/46AVQEY

Check out this free white paper on how #GOWIN is addressing data aggregation communication challenges in battery-powered, space-constrained environments. GOWIN's GW1NZ FPGA devices present an innovative solution, offering ultra-low power consumption, compact form factors, and versatile capabilities for seamless data aggregation. This white paper explores the features, applications, and advantages of GW1NZ FPGA devices in addressing these challenges. View our White Paper here: https://lnkd.in/gmYxrDEW

Demos set up and running: - Person recognition and license plate recognition using our #vectorblox #machinelearning accelerator - H.264 encoding on our entry-level DISCO-KIT - Aurora running at 6 Gbps between a PolarFire board and a #kria SoM, using IP from A.L.S.E. (www.alse-fr.com), provided by Bertrand Cuzeau - Face, hand and body #recognition using a partner solution, optimized die performance and low power, run by Lorant Bartha - #motorcontrol on FPGA on SmartFusion2 - #opcua on PolarFire #soc - Low latency Sobel filtering on a module from Enclustra, important: without any heatsink or fan. For those of you that like a challenge: we have one board on the tables with a fan (not counting laptops). Can you find it? For those of you present at #fpgaconference organised by ELEKTRONIKPRAXIS and PLC2 , drop by and win something. #fpga

Exciting times in the world of FPGA development! 🚀 Just wrapped up a seminar on Vitis HLS and Kria, exploring the cutting-edge technologies that are shaping the future of hardware acceleration. 💡 It was a pleasure sharing insights and knowledge with fellow enthusiasts. Special thanks to everyone who joined in and contributed to the discussion. Let's keep pushing the boundaries of FPGA innovation together! #empaElektronik

We're excited to announce the release of the FPGA bitstream for Infinite-ISP, designed for the Kria™ Vision AI Starter Kit (KV260). Infinite-ISP streamlines ISP development, guiding you from algorithm development through to RTL design, all the way to FPGA/ASIC implementation. Key Features Include: - Fully functional 10-bit ISP - Integration with the AR1335 image sensor - Output resolutions of 1080p and 360p at 30fps - Tuned for indoor applications What's Next? We are working on introducing even more features, including support for the OV5647 image sensor and YUV output! Seeking collaborations from engineers, industry experts, and tech enthusiasts to: 1. Dive in and assess the Infinite-ISP. 2. Share your invaluable feedback. 3. Contribute and co-create. Let's drive this initiative forward, together! Discover more and access resources: https://lnkd.in/duzfhTZn Kudos to our dedicated ISP team at 10xEngineers for turning this vision into reality. Here's to reshaping the ISP landscape, hand in hand! #InfiniteISP_FPGA #ISP #imagesignalprocessing #imagesensor #RTL #FPGA #ASIC Xilinx

FREE Online Workshop: Designing with the AMD Versal Adaptive SoC: Network on Chip April 18-19 2024 - Americas Registration Link: https://lnkd.in/gjdbNDy5 More information: Designing with the AMD Versal Adaptive SoC: Network on Chip ONLINE WORKSHOP (doulos.com) This workshop (delivered in 2 half day sessions) introduces the Versal adaptive SoC Network on Chip (NoC). Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device. The workshop is designed to maximize individual engagement and learning. Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process. #amd #xilinx #free #workshop #online #virtual #versal #adaptivesoc #noc #networkonchip #soc #fpga #doulos #fastertechnology

Today in QEC on the arXiv: A new clustering decoder from Riverlane https://lnkd.in/eQW7y96M With similarities to Union Find (and HDRG decoders before it) but with a focus on being as lean and fast as possible and running on FPGA and ASICs. Results are presented for surface codes.