In this article, explore the design and functionality of a digital shift register intended for use in mixed-signal circuit simulations in #LTspice Read More ⬇️ https://bit.ly/3VYHoCu
All About Circuits’ Post
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Taking on the Q from Qorvo, the latest iteration of SPICE is QSPICE. QSPICE is the work of creator Mike Engelhardt, who also developed LTspice®, the industry’s most widely used version of SPICE. Like LTSpice, QSPICE has no use restrictions and no limits on nodes, components, or subcircuits. QSPICE also improves design productivity by increasing simulation speed, functionality, and reliability. Qorvo says QSPICE can reduce simulation run times and achieve a 100% completion rate. QSPICE can also help engineers analyze power integrity and noise in power management and mixed-signal designs where these are critical metrics, especially for SiC-based devices that operate at high frequencies. It simulates parasitic impedances in interconnections and power delivery networks to analyze power integrity in a circuit. It does this by using netlists extracted from other tools or its own calculations from dimensions and metal alloy data. What I like most about QSPICE, is that you can create your own operating algorithms such as a black box or a neural network in C code to implement it in your circuit, in this way, you can create the datasheet of any electronic component and implement it in your circuit
What You Need to Know About SiC and Qorvo’s QSPICE Simulator
https://rfmwblog.com
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Exciting news: I immediately built up a first thermistor model dedicated to this software (on hackster.io) and plan to write some more. This is especially interesting as QSPICE allows digital simulations, and not only analog.
Qorvo's QSPICE Is a Free Next-Generation Mixed-Mode SPICE Simulation Tool
hackster.io
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Our friends at MathWorks interviewed our Jens Mellberg about how we work with Simulink in baseband and RF Design. Read the article here: https://lnkd.in/d_QFQs4t #shortlink #asic #asicdesign #SiliconIP #EmbeddedSystems #SubGHz #mixedsignal #RFDesign #mathworks #simulink #matlab
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My first IEEE Access journal article publication. Hope you enjoy reading it. 🤗 Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it’s one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first-order Low Pass Filter (LPF). The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by the User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the Multi-stAge noiSe sHaping (MASH) 1-1-1 topology to generate the fractional part. Modelling non-linear effect like the phase noise of each sub-block, which is converted to the Root Mean Square (RMS)-jitter, by using the ‘class’ datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, taking the loading effect due to capacitances and resistances at the output by using the User-Defined Resolved Nets (UDRN). The simulation results ensure that there is an accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used. There is a video attached with the paper, illustrates why the SystemVerilog HDL is chosen to model the analog devices in the digital environment. Moreover, the video highlights the tools used during Simulation (QuestaSim) and during debugging (Questa Visualizer Debug Environment).
Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator
ieeexplore.ieee.org
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For most of its history, #ansys has focused on simulations of components or parts and the physics they experience. As we evolve our codes and take advantage of new compute hardware (#gpu) , we are seeing more and more the simulation of products interacting with the larger environment they are operating in. I am super excited to see a new offering called "RF Channel Modeler" enable our customers to simulate "things" moving around dense 3D/urban environments. We can now handle Radar/EM simulations in near or actual real time, at huge scales, moving around with time stamps. Broad band, full EM/wavelength data just as if you were measuring it in the real world. So cool and super impactful for #5G and #6g systems that will be moving around us very soon! https://lnkd.in/g6eRyir4
Ansys Enhances Mission Modeling with Cesium
cesium.com
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Check out this video (https://hubs.la/Q027Gy8p0) to see how to use the Immersed Boundary Method (IBM) in SimScale. IBM is based on a cartesian grid in which the geometry is immersed into, making the mesh resilient to geometrical details. The model also does not require CAD simplification. #electronics #CFD #engineering #simulation
Thermal Simulation With Immersed Boundary Method | Webinar
https://www.simscale.com
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Check-out how X-Pessimism in Xcelium increases the accuracy of RTL simulation, aligning it with real hardware behavior
Be Optimistic About Xcelium's New X-Pessimism App!
community.cadence.com
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Gate-level simulation has many benefits, but we also all know the pain of trying to run it. Setting up and running GLS on large designs is a huge time sink for engineers. Learn how a team at Northrup Gruman used speedy gate-level simulation with Xcelium Multi-Core. https://lnkd.in/dcXnnEkK
Speedy Gate-Level Simulation with Xcelium Multi-Core - Northrup-Grumman's Story
community.cadence.com
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Predicting VDS switching spike with SPICE simulation Article By: Andrew Cheng and Chun-Shih (Lion) Huang, Monolithic Power Systems, Inc. This article discusses the effect of parasitic inductance on the VDS switching spike while showing how to prevent an avalanche breakdown on the MOSFET. https://lnkd.in/gtmPFJct
Predicting VDS switching spike with SPICE simulation - EDN Asia
https://www.ednasia.com
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When I designed the mixed-signal boundary handling in Verilog-AMS (decades ago), one of the goals was to be able to back-annotate SPEF into behavioral modeling so that we would get accurate power and timing numbers (for digital and analog). Since these guys don't seem to be on top of that I'd suggest they aren't really "experts". If you want a simulator that does this stuff properly, get in touch with a real expert (me). https://lnkd.in/grJtN7q3
Analog Design Complicates Voltage Droop
https://semiengineering.com
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