Physical Design Verification Engineer

Physical Design Verification Engineer

We're working with an innovative and well-funded hardware startup in Silicon Valley looking for a Physical Design Verification Engineer. They are looking to redefine silicon technology with Risc-V based computing platforms that will revolutionize the industry. A great opportunity to collaborate with some of the most talented and passionate engineers globally to design systems that excel in performance, energy efficiency, and scalability.

Responsibilities

• Develop and enhance our PDV methodology and infrastructure for verifying large SoCs.
• Perform full chip integration and run comprehensive physical verification checks.
• Guide implementation teams to ensure early convergence and final project closure.
• Interface with various internal and external design teams to ensure high-quality deliverables and successful integration.
• Collaborate with packaging and floorplanning teams to design padring and bump maps.
• Work with the technology team to define workflows and integrate foundry PDK data.

Requirements

• In-depth understanding of challenges with deep sub-micron process nodes.
• Hands-on experience with closure and tapeout of large hierarchical designs.
• Proficiency with industry-standard physical verification tools (e.g., Siemens Calibre).
• Strong scripting skills in Tcl and Python.
• Excellent problem-solving abilities, communication skills, and organizational skills.
• Self-motivated and highly driven.
• Ability to work cross-functionally with various teams and meet aggressive schedules.