Execute design planning tasks including partitioning, bump planning, and routing strategies.
Demonstrate proficiency in Static Timing Analysis (STA) to ensure design meets timing requirements.
Utilize strong debugging skills to identify and resolve design issues efficiently.
Integrate analog blocks into the digital design flow.
Implement low power design techniques to optimize power consumption.
Perform signoff checks including Logic Equivalence Checking (LEC) with Conformal, RTL Versus (RV) analysis with Ansys tools, Layout Versus (LV) with DRC clean-up utilizing Caliber, and Voltage Constraint Logic Planning (VCLP) with static checks.
Drive timing closure through Physical ECO (Engineering Change Order) and Tweaker methodologies.
Qualifications
Bachelor's or Master's degree in Electrical Engineering or related field.
5-10 years of experience in physical design, with a strong understanding of RTL to GDS flow.
Proficiency in Fusion Compiler, Cadence Innovus, and other relevant EDA tools.
Thorough understanding of macro placement, floorplanning, CTS, and routing techniques.
Experience with STA and timing closure methodologies.
Knowledge of analog block integration and low power design principles.
Familiarity with signoff checks including LEC, RV, LV, and VCLP.
Excellent communication skills and ability to work effectively in a team environment.
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Engineering
Industries
IT Services and IT Consulting
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