Physical Design Engineer

This hardware startup in Mountain View, CA is on a mission to become THE computing platform for AGI. Founded by highly respected engineers that were instrumental in Google’s AI capabilities. They are building hardware by combining deep domain experience for large language models, graphics processing units and other machine-learning models, enabling developers and programmers to make artificial intelligence better, faster and cheaper.

They are looking for a Principal Level Physical Design Engineer to join their team and help develop top-tier silicon for high-performance and sustainable GenAI. In this role, you will be instrumental in delivering high-performing and functionally accurate silicon for their products, covering compute and memory management.

This is a full-time hybrid role (Tues-Thurs) in the Mountain View, CA office.

Compensation: $250k-$300k + equity + benefits

Job Responsibilities

• You will develop and enhance silicon design and physical design methodologies, creating scalable solutions for blocks, subsystems, and full chip designs from RTL to GDS.
• You will take ownership of entire subsystems or specific subsets and chip-level physical design tasks, including floor-planning, placement, clock insertion, routing, optimization, timing closure analysis, physical verification closure, and electrical analysis.
• You will plan and lead intermediate and final reviews, as well as track execution progress using key PPA metrics, ensuring milestones such as design freeze and tapeout are met.
• You will collaborate closely with design, DFT, and other physical design team members to achieve top-tier performance, power, and area results for the subsystem or block.
• You will coordinate with design services partners and critical third-party vendors to plan and execute block-level and chip-level closure for the blocks you manage and oversee.

Job Requirements

• Minimum 8 years of industry experience in ASIC Physical Design
• Proven track record in floorplanning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off, and related areas, ensuring tapeout-ready GDS for large physical blocks and/or top-level designs.
• Demonstrated ability to collaborate with design, verification, and DFT teams to structure and partition designs optimally for PPA and sign-off.
• Experience working with third-party design services partners, taking subsystems and/or top-level designs from initial floor plan to sign-off and tapeout, is a plus.

All candidates must be authorized to work in the United States and work from their offices in Mountain View Tuesdays-Thursdays.