AI Connectivity Performance Architect

A NauWork semiconductor client is seeking an AI Connectivity Performance Architect to join their Network and Edge products team. This position can be onsite or fully remote.

In this role, you will be defining and developing performance models for networking subsystems in cutting-edge Ethernet network controllers (aka SmartNICs). There will be a focus on modeling behavior at the Register Transfer Level (RTL) in addition to modeling other logic abstraction layers.

You will be using these models, in consultation with architecture and design teams, for pathfinding and behavior analysis at the early stages of projects.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Software Engineering, Computer Science, Math, or in a similar field of study and 6+ years of experience
• 6+ years of experience in performance modeling, with strong experience in RTL modeling (Verilog).
• 6+ years of networking experience, including experience with RDMA and other high-performance networking technologies and concepts.
• 6+ years of experience in SystemC programming
• 3+ years of experience in C/C++ programming
• 3+ years of experience in Python scripting
  
  
  

Preferred Qualifications:

• Post-degree in Electrical Engineering, Software Engineering, Computer Science, Math, or in a similar field of study and 9+ years of experience
• Experience with performance modeling for network I/O (eg PCIe bus) and network on chips (NoC)
• Experience in Logic Design performance verification
• Machine learning modeling experience is preferred