Jeff Liu

• Designed Ecommerce website for users to login; log out; shop and checkout products; view orders, for admins to update products, orders, and users’ info with React.js, Next.js as Frontend, Node.js, Express.js, MongoDB as Backend;
• Enabled Both Firebase and JWT_COOKIE Authentication for users;
• Integrated third party payment and Email sender APIs from Stripe and SendGrid;

• Designed travel website enabling users to login; log out; book tours; check orders, comment on tours; admins to manage tours, users, and reviews with Frontend Pug, Axios, Backend Node.js, MongoDB, and Express.js;
• Created user JWT_COOKIE Authentication by Node.js middleware;
• Integrated third party payment and Email sender, and Geo Information from Stripe, SendGrid, and Mapbox

• Built the Android Application for users to obtain prefer location’s weather data in two weeks with daily notification about the current weather info.
• Designed data model with SQLite and Content provider with the weather data query from OpenWeather Website API; Created Restful API for CRUD operations on database.
• Added Firejob-dispather API to send notifications in backend for updating weather information.
• Integrated address information, latitude, longitude based on Google… Show more

• Built the Android Application for users to obtain prefer location’s weather data in two weeks with daily notification about the current weather info.
• Designed data model with SQLite and Content provider with the weather data query from OpenWeather Website API; Created Restful API for CRUD operations on database.
• Added Firejob-dispather API to send notifications in backend for updating weather information.
• Integrated address information, latitude, longitude based on Google GeoLocation API to update location.
• Tested the application functionalities with JUnit and Travis.ci
Show less

Building the basic five components for processors: Program counter; Instruction Memory;Register File;ALU;Data Memory; Based on System verilog/ Quartus II environment
Pipe-lining five stages with four registers with the main control signals for each control units generating during the Ref/Dec stage; Control signals for Exec(ALUOp,ALUSrc) are used 1 cycle later; Control signals for Mem(MemWE, Mem2Reg) are used 2 cycles later; Control signals for Wr(RegWE) are used 3 cycles… Show more

Building the basic five components for processors: Program counter; Instruction Memory;Register File;ALU;Data Memory; Based on System verilog/ Quartus II environment
Pipe-lining five stages with four registers with the main control signals for each control units generating during the Ref/Dec stage; Control signals for Exec(ALUOp,ALUSrc) are used 1 cycle later; Control signals for Mem(MemWE, Mem2Reg) are used 2 cycles later; Control signals for Wr(RegWE) are used 3 cycles later)
Implementing NOOP for both Mem and Writer back for conditional branch; Using Stall, or branch prediction to deal with the problem that branch updates the PC at the end of Reg/Dec stage; Creating forwarding data strategies to deal with data hazard problem
Implementing the direct Mapped L1 cache and two-way Set Associative L2 Cache (Write through between each cache)
Testing the CPU with 300 different machine code (benchmark); Converting into assembly languages involving AddiB;AddsSubs;CbzB;LdurStur;Blt;MovkMovz;LdurbSturb;forwarding Show less