Tyler James Johnson

A method performed by a processor in a hybrid cloud environment, the method including: specifying at least one service provider zone associated with a resource or a service of a service provider, the service provider zone including a first management interface node corresponding to the service provider; specifying at least one data center zone associated with a set of services or resources located near one another, the data center zone including a second management interface node corresponding… Show more

A method performed by a processor in a hybrid cloud environment, the method including: specifying at least one service provider zone associated with a resource or a service of a service provider, the service provider zone including a first management interface node corresponding to the service provider; specifying at least one data center zone associated with a set of services or resources located near one another, the data center zone including a second management interface node corresponding to the set of services or resources; receiving, by the first management interface node, information from the resource or service associated with the at least one service provider zone; translating, by the first management interface node, the information from the resource or service to a format understandable by the second interface node to create first-level translated information; and transmitting the first-level translated information from the first interface node to the second interface node. Show less

In an illustrative implementation, a system for testing a scalable computer system includes configuring a single cell on a partitionable system to create an isolated test channel. A test packet is generated and provided to the test channel. The test channel inserts the test packet into the scalable computer system via a communications link, and a response to the insertion of the test packet is monitored to determine system performance.

A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status informati

A system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

A system includes a monitoring system that provides at least one signal as a function of at least some data provided on a bus. A measure of performance for the at least some data is adjusted based on the at least one signal.

A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation circuitry is in communication with the data in order to provide to the performance counter a validation signal indicative of the validity of the data.

A system and method for detecting an edge of a data signal carried on an observability bus. In one embodiment, a first performance counter is connected to receive the data signal in order to assert a trigger signal in response to detecting an assertion of the data signal. A second performance counter is connected to receive the data signal and the trigger signal. The second performance counter detects the edge responsive to detecting the assertion of the data signal and a logic level in the… Show more

A system and method for detecting an edge of a data signal carried on an observability bus. In one embodiment, a first performance counter is connected to receive the data signal in order to assert a trigger signal in response to detecting an assertion of the data signal. A second performance counter is connected to receive the data signal and the trigger signal. The second performance counter detects the edge responsive to detecting the assertion of the data signal and a logic level in the trigger signal that is a complement to a logic level associated with the assertion of the signal.

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In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits ("MSBs") of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.

A general purpose performance counter ("GPPC") connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value… Show more

A general purpose performance counter ("GPPC") connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set. Show less

A method of optimizing post-silicon test coverage for a system under test ("SUT"). The method comprises defining coverage data comprising Hardware Description Language ("HDL") events; testing the SUT using a system exerciser connected to the SUT; comparing the results of the testing with the coverage data to identify underutilized areas of functionality of the SUT; and responsive to the comparing operation, performing additional tests.

A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer ("DEMUX") which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer ("MUX") comprising M inputs, wherein each of the M inputs is connected to one of the registers.

In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask ("mmask").

One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.

A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for receiving a copy of the N times duplicated signal; and an OR gate having a plurality of inputs, wherein each input of the OR gate is connected to an output of one of the AND gates, wherein an output of the OR gate comprises the corrected signal.

In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to… Show more

In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to be observed responsive to occurrence of the at least one specified condition is logged in the second log.

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An integrated circuit ("IC") comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.

A bus interface module ("BIM") connectable to a debug bus is described. In one embodiment, the BIM comprises a plurality of BIM segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising logic for receiving data from a previous BIM, logic for receiving data from local logic associated with the BIM, and logic for combining the previous BIM data with local logic data and transmitting the combined data to a next BIM.

In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator… Show more

In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address. Show less

A method of processing a database comprising information regarding hardware design language ("HDL") events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries,… Show more

A method of processing a database comprising information regarding hardware design language ("HDL") events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries, wherein each of the entries corresponds to one of the signals observed on the observability bus and contains signal information pertaining to the one of the observed signals. Show less

In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.

A method, system, apparatus and supporting ontology for a hybrid cloud integration fabric (HCIF) may be provided. According to some aspects of the present disclosure, the HCIF can provide an extensible programming framework and data model (ontology) for integration, orchestration and management of one or more heterogeneous cloud services and on-premise environments.

One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least… Show more

One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states. Show less