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Experience & Education
Publications
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New Clockwork: Time in CPUs
The NITRD National Workshop on The New Clockwork for Time-Critical Cyber-Physical Systems
Enabling time in CPUs and Processor Interconnects in Cyber Physical Systems allows higher precision in IO synchronization and improves reliability and precision of the global schedule
Other authorsSee publication
Patents
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Graphical Development and Deployment of Parallel Floating-Point Math Functionality on a System with Heterogeneous Hardware Components
Issued US 9,235,395
The present invention relates to the field of programming, and more particularly to development and deployment of parallel floating point math functionality on a system with heterogeneous hardware components, and global optimization of programs with floating point math functionality. Respective portions of the program for respective deployment to respective ones of the heterogeneous hardware components may be automatically determined, including determining respective execution timing for the…
The present invention relates to the field of programming, and more particularly to development and deployment of parallel floating point math functionality on a system with heterogeneous hardware components, and global optimization of programs with floating point math functionality. Respective portions of the program for respective deployment to respective ones of the heterogeneous hardware components may be automatically determined, including determining respective execution timing for the respective portions. The method may also include automatically generating at least one hardware configuration program from the program and the first program code, including compiling the respective portions of the program and the first program code for deployment to respective ones of the heterogeneous hardware components. The hardware configuration program may be directly converted into a hardware configuration program, e.g., an FPGA program file, describing a plurality of computing elements, including, for example, but not limited to, one or more of: fixed point FPGA fabric, floating point FPGA fabric, DSP cores, soft or hardcore microprocessors, graphics processing units (GPUs), or other heterogeneous computing elements which are integrated in one heterogeneous or homogenous chip or chipset or multiple heterogeneous or homogenous chipsets. The above techniques may also be applied to real-time or faster than real-time simulation, as well as global optimization of system designs via such simulation.
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Developing programs in a graphical specification and constraint language
Issued US 8,726,228
System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and…
System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are usable to analyze the graphical program or generate a program or simulation.
Other inventorsSee patent -
Developing programs for hardware implementation in a graphical specification and constraint language Via iterative estimation of performance or resource utilization
Issued US 8,719,774
System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and…
System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation
Other inventorsSee patent -
Graphically representing timing in a graphical program
Issued US 8,397,205
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one…
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
Other inventorsSee patent -
Timing wires in a graphical program
Issued US 8,359,567
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one…
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
Other inventorsSee patent -
System and method for converting graphical programs into hardware implementations which utilize probe insertion
Issued US 6584601
A method for generating a hardware implementation of graphical code. Produces FGPA implementations of LabVIEW programs (LabVIEW FPGA).
Other inventorsSee patent
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DDI Management Training
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Spanish
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German
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Association for Computing Machinery (ACM)
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