Homer Antoniadis

Efficient Power Conversion Corp (EPC), headquartered in El Segundo, CA, specializes in gallium nitride on silicon (eGaN) power FETs and integrated circuits for power management applications, with recent validation of their GaN intellectual property rights by the US International Trade Commission (ITC). The ITC upheld EPC's patents and found Innoscience Technology Co Ltd guilty of infringing EPC’s foundational patent, potentially leading to a ban on importing their products into the USA. This ruling is a significant validation of nearly two decades of EPC's hard work and research, reflecting the importance of their intellectual property portfolio. The ITC's final determination is expected on November 5. Innoscience EPC - Efficient Power Conversion #semiconductor #intellectualproperty #industry #lawsuit #technology #GaN https://lnkd.in/di792VMW

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The semiconductor and hardware industries are becoming more global and in the past twelve months, I’ve seen evidence of this firsthand by having probably a dozen conversations with foreign startup leaders who wanted to expand their design centers in North America, with a particular emphasis on Canada. Part of this shift is the economics of capital. North America has one of the richest investment capital markets and is home to some of the most prolific startup venture capital organizations in the world. In addition, and just as important, these companies wanted access to the best talent, which often meant they needed to look at geographies with deep talent pools, establish their presence, and ramp up operations by doing an acqui-hire or a team extraction. Canada boasts an exceptional hardware talent pool, owing in part to their top universities and immigration policies that are more favorable than those in the US. Canada’s trade policies also create easier ingress for these companies to enter the North American market when they’re ready to commercialize. During a recent conversation with Hugh Chow, CEO of ventureLAB(Canada’s premier hardware startup accelerator), we discussed why Canada is such an attractive destination for innovative companies that want access to capital and world-class talent. Hugh also explained the role that VenureLAB plays in helping these hardware startups. I’m grateful to Hugh for sharing his insights and I believe that by shining a light on the talent and resources Canada has to offer, Hugh and his team at VentureLAB will empower many founders and help their innovative ideas take flight. Hugh will be joining me and two other luminaries, Raymond Chik and Richard Fung in July for a panel discussion about the Canadian hardware ecosystem. Stay tuned for more details about that. If you’re a leader who is looking to start an office in Canada and you want to explore options to identify a senior leader, or, if you're interested in the aforementioned acqui-hire or team extraction, I can be reached for a confidential discussion here: 📞602-368-5555 📨 jkinsey@sbtindustries.com #semiconductorindustry #talentacquisition #recruiting

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Last week’s DAC showcased exciting announcements from startups that are revolutionizing semiconductor design however these rising stars overshadowed a major update from an industry stalwart - Alphawave Semi - whose news is poised to accelerate the proliferation of chiplets and give rise to a “chiplet marketplace”. Alphawave Semi announced a breakthrough with the tapeout of the industry's first off-the-shelf, multi-protocol I/O connectivity chiplet. This technology can seamlessly integrate into larger SoCs or multi-chip modules, giving designers increased flexibility and more connectivity options for different applications. Reflecting on the Chiplet Summit this past spring, I remember listening to Tony Chan Carusone, Alphawave’s CTO, as he passionately described the significance of chiplets and how Alphawave will foster a more open and democratic design ecosystem. Now, just one quarter later, his team has launched a technology that brings this vision much closer to becoming a reality. Adding to their momentum, Alphawave also announced an expanded partnership with Samsung Foundry to advance the industry's progression toward cutting-edge semiconductor nodes, crucial for the evolution of advanced compute. Samsung’s roadmap in sub-4nm technologies includes FinFET and Gate-All-Around, which are designed to maximize performance in the post-Moore era. Initially targeted for data centers and HPC, these innovations may trickle down to low-cost, AI-enabled edge devices, putting the transformative power of AI into the hands of billions of people worldwide. This news follows Alphawave’s early June announcement of their new partnership with Arm, aimed at unlocking the potential of processors. Alphawave will give Arm access to their robust portfolio of connectivity solutions and silicon IP, which Arm will integrate into their proven portfolio of compute cores. At a time when AI technology is accelerating at breakneck speed, many companies are searching for ways to boost compute performance and address the challenge of moving data between compute and memory more efficiently. While multiple startups offer unique solutions, many customers want battle-tested technology to avoid the risk of investing in solutions that may become obsolete by the time they reach tapeout. Alphawave has developed vital solutions and in doing so, has increased design flexibility, built bridges to new process technologies, and shortened the path to market. “Connectors” are often the catalysts of innovation and Alphwave’s is a testament to that word. I’m encouraged by what I’ve seen from Alphawave and strongly believe they stand at the forefront of an emerging chiplet marketplace. More broadly, I believe their technology serves to democratize design technology and will give emerging companies more options to bring their brilliant ideas to life. #semiconductorindustry #ai #chiplets

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Thermoelectric thermal stabilizer for circulating fluid RRC-600-TE-LL liquid-to-liquid family. Laser technologies of microelectronics using the example of processing the most important electronics material, which remains silicon.  The advantages of laser technology become clear when new varieties are used, which involve fairly narrow “process windows” using complex nonlinear effects: the use of multiphoton absorption, filament, thermal spalling or “hidden” internal separation. These new technologies make it possible to dramatically reduce the size of defective zones, increase the quality of processing, while simultaneously reducing the width of the cut between chips (from 50–100 to 10–20 microns), which makes it possible to move to new architecture options or increase the density of chips on the wafer. Another option for laser technology is through drilling holes in a silicon wafer (Silicon Through Via), as well as precision laser milling and the formation of complex structures. These capabilities are significant for modern 3D assembly and micromechanical device (MEMS) designs. Laser technology makes it possible to achieve high quality holes, as well as a high ratio of hole diameter to depth, has no analogues from mechanical operations and in many cases is an interesting alternative to plasma-chemical etching. The high stability of the laser beam directly depends on the precise thermal stabilization of the light source. A new thermoelectric thermal stabilizer for circulating fluid RRC-600-TE-LL is developed and manufactured by Crystal Ltd. company for the fast-growing market of micro processing equipment, in particular for tasks in the micro- and electronics industry. The advanced solutions implemented in this device allow: - cool the circulating liquid, maximum cooling capacity 600W, - heat the circulating liquid, maximum cooling capacity 1000W, - stabilize the temperature of the circulating fluid with an accuracy of +/-0.02⁰С in the range from  +5⁰С to +60⁰С,  - noise level 42 dB  - control and monitor from a PC via the RS-485 interface or USB port using the Modbus-RTU protocol,  - carry out adjustment using a built-in temperature sensor or a sensor located directly at the cooled unit,  - automatically calculate setpoint offsets based on the temperature difference measured by the internal sensor and the external sensor,  - place the chiller in a 19” rack in laboratories and clean rooms,  - emergency stop in the following cases: the coolant temperature goes out of the specified range, the temperature sensor breaks, the coolant level in the tank drops below the minimum permissible, or there is no flow.  https://lnkd.in/eusrhQrt

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Jim Keller, former Intel, AMD, and Tesla engineer, aims to challenge Nvidia's dominance in AI with Tenstorrent's energy-efficient chip design. Tenstorrent's upcoming second-generation AI chip promises superior energy and cost efficiency, presenting a viable alternative to Nvidia's offerings. The innovative design of Tenstorrent's chip features independent decision-making cores, potentially reshaping AI chip technology across diverse applications. #AI #Nvidia #semiconductor #semiconductors #chip #technology #innovation #research #computing Tenstorrent NVIDIA https://lnkd.in/g6a3vAu4

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Enabling 2.5D/3D Multi-Die Package Both approaches to integrating multiple #chiplets have unique challenges 💡 In the rapidly evolving world of #ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of #IC design #innovation but also an increased complexity in coordination and integration. At the forefront of this technological revolution is Global Unichip Corp. (GUC), which has effectively harnessed the power of Synopsys Inc’ 3DIC Compiler, a unified exploration-to-signoff platform, to streamline its #chip design processes and reduce overall cycle time. GUC recently presented their multi-die tape-outs at SNUG Silicon Valley 2024, which were made more efficient by Synopsys’ 3DIC Compiler through the implementation of die floorplanning and related bump assignments. 3DIC Compiler helped further check the physical and logical connectivity, sync up information from die to die quickly, and, ultimately, shorten chip design cycle timelines for GUC’s 2.5 and 3D #CoWoS designs. This distinction between 2.5D and 3D IC design approaches becomes critical in addressing the increasing demand for higher performance and more integrated systems. Each method comes with its unique set of challenges and benefits, tailored to specific application needs. Thanks again to Kenneth Larsen and Semiconductor Engineering for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/e48EXEFw #semiconductorindustry #semiconductor #foundry #advancedpackaging #technology #icdesign #usa #chip #tech #semiconductormanufacturing

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GlobalFoundries Acquires Tagore Technology’s GaN Technology to Accelerate Disruptive Power Management Solutions. My thought on this acquisition: When selecting foundry partners for GaN (Gallium Nitride) power devices, several key criteria are typically considered to ensure the foundry can meet the specific requirements of GaN power semiconductor production. Here are the primary criteria: technical capabilities, quality and reliability, manufacturing capacity, cost consideration, geographical location, IP protection, R&D support, supply chain integration, and sustainability practice. Currently, the major GaN fabless players use the foundry such as TSMC and Episil. This acquisition will provide GaN fabless players with an additional option to expedite their product releases and expand into markets beyond consumer electronics, such as data centers and humanoid robots. #AI #GaN #GlobalFoundries #Data Centre #Sustainability

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Bump Pitch Transformers Will Revolutionize Advanced Packaging There’s better, cost-effective path to 2.5D packaging landscape SAN FRANCISCO, June 27, 2024 /PRNewswire/ -- Dr. Larry Zu, Founder and CEO of Sarcina Technology, the Application Specific Advanced Packaging (ASAP) Design Service and Production leader, predicted that recent Bump Pitch Transformer (BPT) designs will speed 2.5D IC advanced packaging adoption to meet the red-hot demand for AI innovation. In remarks made in the Keysight Theater at the 61st Design Automation Conference, he envisioned new BPT technology paving the way for new artificial intelligence computing opportunities. "We believe that the Bump Pitch Transformer architecture will accelerate the growth rate of 2.5D semiconductor packages that are key to meeting the explosive demand for AI-driven computing capabilities," Dr. Zu said during his address in the Keysight Theater. Fan-Out Chip-on-Substrate with Silicon Bridge (FoCoS-B) is the latest BPT advancement, he said, and it democratize the 2.5D era. This packaging technology is now available through companies such as ASE and SPIL, breaking a logjam of innovation created by previous proprietary BPT technologies. FoCoS-B is a silicon bridge technology, replaces expensive silicon TSV interposers with more cost-effective re-distribution layers (RDL). This architecture is ideal for homogenous and heterogenous chiplet integration targeting high-performance computing (HPC) devices for AI, data center, microprocessor, and networking applications. Current advanced 2.5D packaging uses a substrate to transpose an IC's microbump pitch from 40-50 um to the package's 130 um bump pitch. These substrates are very expensive, in short supply, and are complex to design resulting in lead-time and cost challenges. The new FoCoS-B technology is effectively a Wafer Fan-out RDL technology which, due to its maturity, has inherently a lower cost and shorter lead time thus enabling system designers to optimize AI for new lower cost applications. Sarcina is currently engaging companies with two Bump Pitch Transformer derivatives across a range of applications. Its services include BPT interposer design, O/S test pattern insertion, fabrication & BPT wafer sort, along with package substrate design, PI/SI + thermal system simulation, & substrate fabrication. A complete WIPO (wafer in, package out) engagement also covers package assembly, final test, and production services. The company has had a number of 2.5D customer devices to successfully enter production going back several years, including a large 47.5 mm x 47.5 mm, 2,019 ball high performance flip chip ball grid array device. (for further reading, please go to )

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A very interesting blog by Giuseppe Piccolboni of Weebit Nano Ltd about the use of our #ReRAM for #neuromorphic applications

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https://lnkd.in/ethDyF98 Anis Rahman Chief Technology Officer, President Applied Research & Photonics, Inc. Harrisburg, PA, United States Silicon carbide (SiC) is an important semiconductor for high temperature and high voltage applications such as in electric vehicles. The SiC boule is grown by seeded sublimation deposition process where the primary ingredients viz. carbon (C) and silicon (Si) are sublimated at very high temperature. Eddy and Gaskill [1] indicated that the variations in the atomic ratio of Si to C in the vapor phase that arise from feedstock granularity is difficult to minimize during growth. It is also difficult to avoid impurities arising from both in the SiC feedstock and in the graphite-insulation used in the growth reactor. Additionally, radial, and axial thermal profiles in the reactor and boule may cause polycrystallinity, grain boundary formation, and other defects in the lattice, which may lead to macro- and micro-domain formation. Because the understanding of materials’ properties at the extreme growth temperature of ~2200°C is incomplete, the boule growth modeling efforts are based on extrapolated parameters. Thus, an accurate experimental quantification is very important. The evolution of domain walls in single crystalline SiC is therefore very difficult to eliminate, and they stay put in the boule. This paper investigates SiC substrates and epitaxial SiC wafers via cameraless T-ray imaging route. T-ray images reveal significant features that were not seen before. “Dendrimer dipole excitation (DDE)” T-ray source was used that generates wider terahertz bandwidth (0.1 THz to ~30 THz) and generate >200 milliwatts of CW power without requiring a femto-second pulsed laser. An instrument system, the T-ray nanoscanning and 3D imager (TN3DI), has been designed around the DDE T-ray source that was used for the present investigations. Here the wafer was directly mounted on the nanoscanner and the whole wafer was scanned for imaging. T-ray images (see Fig. 1) have revealed some patterns in the SiC wafers of the present investigation that were unseen previously. Optical images and T-ray images were compared side-by-side that shows that the T-ray exhibits higher sensitivity and clearer images thus reveals internal intricate pattern not visible by the optical and X-ray technique. Here, we propose that the unique patterns observed from the T-ray images are due to some kind of domain formation in the boule that has remained in the wafers even after slicing and polishing. This hypothesis is further strengthened via T-ray micrograph of different wafers that exhibit many micro-domains on the epi layer of a 100 mm SiC wafer. Thus, the T-ray images have revealed some intricate patterns for the first time that are present in the SiC wafers. Details of the principle and experimental will be presented.

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Stitching vias, also known as via stitching, are a crucial design practice for PCBs. By placing a series of vias around the perimeter of a ground plane or signal trace, a continuous conductive path is created, connecting the top and bottom layers of the board. #PCBdesign #viastitching

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#HBM Prices to Increase by 5–10% in 2025, Accounting for Over 30% of Total #DRAM Value, Says TrendForce Corporation 💡 Avril Wu, TrendForce Senior Research Vice President, reports that the HBM market is poised for robust growth, driven by significant pricing premiums and increased capacity needs for AI #chips. HBM's unit sales price is several times higher than that of conventional DRAM and about five times that of #DDR5. This pricing, combined with product iterations in AI #chip #technology that increase single-device HBM capacity, is expected to dramatically raise HBM’s share in both the capacity and market value of the DRAM market from 2023 to 2025. Specifically, HBM’s share of total DRAM bit capacity is estimated to rise from 2% in 2023 to 5% in 2024 and surpass 10% by 2025. In terms of market value, HBM is projected to account for more than 20% of the total DRAM market value starting in 2024, potentially exceeding 30% by 2025. A big thank you again to Avril Wu and TrendForce 集邦科技 for the full article with more background and insights via the link below 🙏💡👇 https://lnkd.in/eDC9_Z7u #semiconductorindustry #semiconductors #semiconductor #tech #micron #skhynix #samsung #foundry #innovation #ai #nvidia #tsmc #server #it #ic

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PCIe Gen6 + 5nm + MRVL SerDes = Lowest Power for AI!!

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I've registered for the webinar: Rethinking batteries: exploring batteries' role in the long-duration energy storage landscape (July 11th at 9h PT / 12h ET / 18h CEST) ✅ Join me for this free session for an in-depth exploration of batteries and their significance within the Long-Duration Energy Storage ecosystem ⚡ https://lnkd.in/gDCZzdmY This session is designed to go over the following areas: ✅ Highlight the adaptability of lithium-ion batteries to the long-term energy storage market, including advancements in manufacturing processes aimed at cost reduction, increased production, and the implementation of safety measures to mitigate risks ✅ Explore the potential of other batteries such as flow batteries, such as vanadium redox flow batteries and zinc-bromine flow batteries, which offer inherent advantages for long-term energy storage, including scalability and the ability to decouple power and energy capacities ✅ Showcase case studies illustrating the deployment of these technologies and their impact on long-term energy storage projects Register here 👉 https://lnkd.in/gDCZzdmY RENMAD - Energy Events

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Need for advanced packaging material overhaul due to chiplets and multi-dies: "Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. .. In addition, large foundries and OSATs already have made significant investments in other materials, such as copper clad laminates. Those are field-proven as a base material in PCBs, but they will run out of steam when the packaging industry gets down below 2/2nm lines/spaces. Shifting to glass requires a whole new round of equipment investments and new processes, or some way to combine it with existing processes. .. One of glass’ most attractive features is its low dielectric constant, minimizing signal propagation delays and crosstalk between adjacent interconnects, which is crucial for high-speed electronics. It also reduces the capacitance between interconnects, allowing for faster signal transmission and improved overall performance. In applications such as data centers, telecommunications, and high-performance computing, where speed is of the essence, the use of glass substrates can significantly enhance system efficiency and data throughput. The low dielectric constant also enables better impedance control, ensuring signal integrity across the entire circuit. This is particularly attractive in RF applications, where impedance matching is essential for maximizing power transfer and minimizing signal loss. By providing consistent electrical properties across the substrate surface, glass substrates facilitate the design and fabrication of high-frequency circuits with enhanced reliability and performance. Another key advantage of glass substrates is exceptional thermal stability, which plays a vital role in maintaining device performance under fluctuating thermal conditions. Unlike copper-clad laminate, which can deform or delaminate under thermal stress, glass substrates exhibit minimal dimensional changes over a wide temperature range."

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A report in the #NYTimes today indicates stimulus from #CHIPS Act already appears to be taking effect.  Done right, we could see more than 30% of the most advanced logic devices manufactured domestically by 2032, up from basically zero today. The result is a change in the total percent of semiconductor devices changing from a downward trend towards less than 10% of global #semiconductormanufacturing to more than 14%. While this may not seem like a major change, consider that all global regions are simultaneously investing heavily in production and we begin to understand how significant this reversal actually is. The National Semiconductor Economic Roadmap (#NSER, https://lnkd.in/gtSGMNjt) modeled and predicted these trends almost 18 months ago (Exhibit 3, below) based upon US leadership in manufacturing capacity investments, and how supply chain, entrepreneurship, infrastructure, and workforce development would be the cornerstones of this resurrection. We’ve seen multiple incentives planned, the directives made for a National Semiconductor Technology Center (#NSTC, #NATCAST) and National Advanced Packaging Manufacturing Program (#NAPMP), supplier funding incentives being communicated, and most recently the announcement by #NIST of the CHIPS Manufacturing USA Institute (https://lnkd.in/g_wb5dXG) dedicated to advancing innovation and productivity through digital twinning across the ecosystem to create a global digital twin for manufacturing, arguably this industry’s moonshot! Let’s align around the spirit of this stimulus and regain our leadership position in semiconductor manufacturing. https://lnkd.in/gwCzSJM5

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5 Reasons Why Legacy Nodes Remain Crucial in the 1nm Era? Legacy nodes Typically refer to older, well-established fabrication processes, often at 45 nm or 28nm and larger. 🚀 Cost-Effectiveness: Manufacturing chips at advanced nodes like 1nm is expensive due to the complexities involved. Legacy nodes are a better choice for cost-sensitive applications. Imagine building a high-performance gaming PC vs. a basic office computer. The gaming PC (1nm chip) is expensive with all the latest tech. But a basic computer (legacy node) is much cheaper to make, perfect for everyday tasks like browsing the web. 🚀 Power Efficiency: Smaller transistors in advanced nodes enable faster performance but often come at the cost of higher power consumption. Legacy nodes, with their larger transistors, can be more power-efficient, a critical factor for battery-powered devices like smartphones and wearables. Tiny transistors in new chips are like powerful engines in cars - they work great but use a lot of fuel (battery power). Bigger transistors in legacy nodes are like fuel-efficient car engines - they might not be the fastest, but they use less battery, ideal for things like smartphones and smartwatches that need to last all day. 🚀 Maturity and Reliability: Legacy nodes have been around for longer and have undergone extensive refinement, leading to highly optimized and reliable processes. This maturity ensures consistent performance and fewer bugs, crucial for applications demanding stability. Think of a recipe you've made many times. You know exactly how much of each ingredient to use and how long to cook it for. Legacy nodes are like that tried-and-tested recipe - they're reliable and we know how to make them work perfectly for everyday electronics. 🚀 Compatibility: Not all applications require the bleeding-edge performance offered by 1nm chips. Legacy nodes can integrate well with newer technologies, enabling efficient design of complex systems with a mix of performance requirements. Imagine building a house - you might need different materials for the roof, walls, and foundation. Legacy nodes can be like those different materials - they work well with newer technologies to create all sorts of electronic devices, like a phone with a powerful processor (1nm chip) but a low-power Bluetooth chip (legacy node) for connecting to headphones. 🚀 Internet of Things (IoT): The vast and growing world of IoT devices, many of them simple sensors, often doesn't need the processing power of 1nm chips. Legacy nodes are perfectly suited for these low-power, low-cost applications. Tiny sensors in things like fitness trackers or smart thermostats don't need the processing power of a fancy 1nm chip. Legacy nodes are the perfect tool for these smaller jobs, keeping costs low and battery life long. Guess, Which Country is investing huge in legacy Nodes? Tell us in the comments. A detailed post is in comments. For all semiconductor and AI content, follow TechoVedas

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SK hynix Achieves 56% Yield in 3D #DRAM 💡 #SKhynix is accelerating its lead in the cutting-edge field of what is often called the "dream #memory," the three-dimensional (3D) DRAM. The company, already a leader in the #artificialintelligence (#AI) #semiconductor market with its high-bandwidth memory (#HBM), is now seeking to continue its innovation in the next-generation DRAM sector. According to industry sources on June 23, SK hynix presented a research paper on 3D DRAM at the prestigious semiconductor conference “VLSI 2024,” held in Hawaii, U.S., from June 16 to June 20. In this paper, SK hynix reported that the manufacturing yield of the 3D DRAM, stacked in five layers, recorded 56.1%. This means that about 561 viable devices were produced out of approximately 1,000 3D DRAMs manufactured on a single test #wafer. The experimental 3D DRAM showed characteristics similar to the currently used 2D DRAM, which was also highlighted in the data presented. This marks the first time SK hynix has disclosed specific figures and operational characteristics of its 3D DRAM development. A big thank you again to Jasmine(영실) Choi(최) and BusinessKorea for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/e-GA9Qpg #semiconductorindustry #semiconductormanufacturing #technology #ai #it #innovation #tech #chip #chips #it #datacenter #computer #chip #ic

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#Intel’s Gary Patton Shows the Way to a Systems #Foundry #61DAC #61DAC was buzzing this year with talk of #AI and multi-die, heterogeneous design. The promise of making 2.5/3D design and a #chiplet ecosystem mainstream reality was the focus of a lot of the panels and presentations at the conference. AI is certainly a driver for this new design style, but the conversation was broader than just AI, as you will see. This new design style will require effort from every part of the #semiconductor ecosystem, and this focus was on display during DAC. There is a focal point where all this work needs to come together to make it commercially available. That focal point is the foundry, and there was a keynote address on Tuesday morning at DAC that did a great job explaining how to open the door to the future. A very big thank you to Mike Gianfagna and SemiWiki.com for the full article  that explores how Intel’s Gary Patton shows the way to a systems foundry via the link below 🙏💡👇 https://lnkd.in/eVgX8wE8 #semiconductorindustry #semiconductors #semiconductor #technology #it #tech #innovation #semiconductormanufacturing #chip #chips #ic

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