About
Low Power design and…
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It was great catching up with the Indian Cricket Legend Sunil Gavaskar Sir and the USA Cricket sensation Saurabh Naresh Netravalkar yesterday. Thank…
It was great catching up with the Indian Cricket Legend Sunil Gavaskar Sir and the USA Cricket sensation Saurabh Naresh Netravalkar yesterday. Thank…
Liked by Harsh Chilwal
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🚗 Retail sales were flat in June, dragged down by #motor vehicle sales that fell -2% despite dealer discounts. The culprit? A #cyberattack that…
🚗 Retail sales were flat in June, dragged down by #motor vehicle sales that fell -2% despite dealer discounts. The culprit? A #cyberattack that…
Liked by Harsh Chilwal
Experience & Education
Patents
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Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design
Issued 11797742
A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value…
A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.
Other inventorsSee patent -
Retention model with RTL-compatible default operating mode
Issued US10769329B1
A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's…
A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command. Restrictions prevent modification of the sequential block and path control signals and prevent use of generic input signals by the retention controller block.
Other inventors -
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Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
Issued US20070047594A1
Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The…
Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
Other inventorsSee patent -
METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
Issued US7546566B2
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
Other inventorsSee patent
Honors & Awards
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Synopsys Excellence Award 2013
Synopsys
More activity by Harsh
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Never thought in our SSPMS days that I would be meeting Prashant Naik & Chetan Suryawanshi in Texas some day. What a journey it has been for…
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In 2018, we started CricKingdom Cricket Academy in Singapore with a dream and passion for the game. Today, in 2024, reflecting on our journey fills…
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Congratulations to KPMG, recognized as the top provider for quality in AI advice and implementation services in Source’s annual U.S. survey of senior…
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During my trip to India this week, I had the opportunity to meet with Tata Sons Chairman N. Chandrasekaran and Tata Electronics Managing Director and…
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Tata Electronics Pvt. Ltd., which is building India’s first semiconductor fabrication plant in Gujarat’s Dholera, has signed a Memorandum of…
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Today, we bid farewell to the Nassau County International Cricket Stadium. The structure will come down over the next few weeks. This is a…
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When you have a tech job and can lead the US to upset Pakistan in the Men's T20 Cricket World Cup in your free time. Legend.
When you have a tech job and can lead the US to upset Pakistan in the Men's T20 Cricket World Cup in your free time. Legend.
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Gathr + Databricks = Massive value * High ROI...at a time when organizations are looking for highest level of productivity while maintaining their…
Gathr + Databricks = Massive value * High ROI...at a time when organizations are looking for highest level of productivity while maintaining their…
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We’re just off the Synopsys Inc earnings call where CFO Shelagh Glaser and I discussed the strong quarter our team achieved in Q2 (snapshot below)…
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