Ali Heydari

I'll see you there! #AI Driving Fabs of the Future...People, Technology, Infrastructure "There has never been a more exciting time in the history of #semiconductor manufacturing. Following the supply chain disruption of the early 2020s, teams rushing to expand operations and add capacity are looking to maximize operating leverage amidst a challenging market backdrop. With dozens of new fully automated 300mm fabs set to open their doors in the next two years, here are the burning questions: -- What does it mean for the existing 200mm legacy fabs?  -- What challenges will we face in 2024? -- How can we solve them together?" SEMI Semiconductor Digest Cadence Design Systems Analog Devices Design News Lin Tso, CMM Samer Bahou https://lnkd.in/gHhJKrEE

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Jim Keller, former Intel, AMD, and Tesla engineer, aims to challenge Nvidia's dominance in AI with Tenstorrent's energy-efficient chip design. Tenstorrent's upcoming second-generation AI chip promises superior energy and cost efficiency, presenting a viable alternative to Nvidia's offerings. The innovative design of Tenstorrent's chip features independent decision-making cores, potentially reshaping AI chip technology across diverse applications. #AI #Nvidia #semiconductor #semiconductors #chip #technology #innovation #research #computing Tenstorrent NVIDIA https://lnkd.in/g6a3vAu4

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As the growth chart for gallium nitride (GaN) wafer demand is looking more like a hockey stick, it’s apparent that innovators who have long believed in the merits of GaN are being proven right. A private company in El Segundo, CA that predates some of the other startups in the GaN-based power IC space by more than a decade has been hard at work developing solutions in this space for over seventeen years. That company is EPC - Efficient Power Conversion and I got a firsthand look at some of their solutions when I was at the 2024 APEC Conference. They were co-founded in 2007 by a luminary of the power IC industry and CEO Alex Lidow. Lidow was at International Rectifier for over thirty years and had leadership positions spanning R&D and manufacturing. He was even their CEO for 12 years. As co-inventor of the silicon power MOSFET in the 1970s, his seminal work has shaped development in this sector. Lidow was flanked by Joe Cao and Robert Beach, both of whom have also made their own impact. Cao had over 15 years of experience and more than 30 patents in developing GaN and silicon power device technologies before deciding to embark on the quest with Lidow. Beach had founded multiple companies aimed at bringing GaN ICs to the marketplace before partnering with Lidow and Cao, making him a perfect complement to their triumvirate. What put EPC on the map was the development of their proprietary enhancement-mode GaN (eGaN) transistors which they released in June 2009. Unlike traditional MOSFETs, which used built-in channels between the drain and source, eGaN MOSFETS had no such channel. eGaN MOSFETs’ have small geometry, low power dissipation, and are easy to manufacture, making them desirable for a wide array of applications. The founders also had the foresight to manufacture using a foundry meant to produce silicon devices and were able to create a mature, efficient, and low-cost supply chain to bring new products to market quickly. Nowadays, newer companies in the space are gaining similar traction using this approach, but it’s safe to say EPC was a pioneer and began to reap the benefits decades ahead of competitors. This is another key element that differentiates them. In my experience, “mature startups” tend to be modest organizations, often letting their technology speak for itself and not over-indexing on marketing their brands to potential talent. But the hiring landscape is far more competitive than it was when they started and the allure of high-growth startups can be attractive for talented engineers. EPC’s goal is to enable companies to develop their technologies by leveraging the power of GaN and avoid being left behind by developing on silicon. That, combined with their lengthy market presence and leadership team, are strong elements to highlight and EPC would be well-served to fold these details into their talent attraction messaging. #semiconductorindustry #galliumnitride #powermanagement

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AI workflows are driving demand for memory and storage to prepare data, train the model and create useful inference engines.  This is driving announcements of storage and memory products that support the various elements of these AI workflows.

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Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. Read this blog to learn more about Verilog-A, the most used language by analog designers to describe analog circuit behavior, representing a high-level abstraction of a semiconductor device. https://ow.ly/yUNr50S5C2f

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Transphorm GaN technology offers the most flexibility in power electronics. This is the result its ease of design, which is one of the cornerstones of our technology. Our SuperGaN FETs compete directly against silicon, silicon carbide, and e-mode GaN whether it’s how the device is driven or the package(s) it’s offered in. Up and above SuperGaN’s flexibility we also enable our SIP (System-In-Package) partners such as Weltrend with GaN FET solutions that compliment our discrete offerings. This results in a solution for all customers no matter their architecture or system needs. #supergan #gan #transphorm #reliability #Weltrend

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https://lnkd.in/gcRMe8Rc Intel’s Latest FinFET Is Key to Its Foundry Plans Company’s new process signals transition toward foundry service provider. #intel #Semiconductorindustry #electronics #semiconductor #supplychain #engineering #manufacturing #computerchips #semiconductors #chips #chipmaker #foundry #technology #innovation #business credit: IEEE spectrum

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In the fiercely competitive semiconductor industry, companies are in a constant battle to retain top talent because in the heart of every good engineer is a passionate problem solver, looking for their next challenge. For them, innovation is the currency of success. Yet companies like Qualcomm, Intel, and Broadcom attract tens of thousands every year by dangling lucrative compensation packages to lure them from competitors. Startup leaders don’t have those resources, so they have to work harder to attract the best talent and then fight like hell to retain them. But some of the most successful startup leaders I know take a different approach. Rather than viewing attraction and retention as a fight, they leverage the inherent qualities of their companies as their advantage. They use their nimbleness, bias toward innovation, and their collaborative cultures like superpowers to attract the right people and those usually end up being the reasons why people stay. Take Richard Fung, CEO of The Six Semiconductor, for example. I had a conversation with Richard and asked him to share his approach to motivating his team. His response was like a mini-masterclass on the topic of talent attraction and retention. Richard emphasized that a culture that encourages engineers to dive deep into the intricacies of their craft, understand the systems they’re building, and connect with the end customer is a successful culture. Richard has been using this approach and it's been paying dividends for The Six Semiconductor so in his honor, here are his six key concepts for creating this type of organization: 1. Foster a Learning Culture: Support ongoing learning and skill development beyond employees' core responsibilities. 2. Prioritize Customer Focus: Embed a customer-centric mindset, and encourage employees to enhance user experiences through their work. 3. Champion Problem-Solving: Empower employees to creatively solve challenges with a focus on customer needs. 4. Promote System-Level Understanding: Encourage employees to grasp the bigger picture of the company's offerings and their role within it. 5. Break Down Silos: Promote collaboration to ensure a comprehensive understanding of projects across teams. 6. Offer Meaningful Challenges: Provide intellectually stimulating projects that make a tangible impact on the company's success. What Richard highlighted is that success goes much deeper than getting great people to join. It's about unleashing the full potential of every individual on your team to drive innovation and help shape the company, and ensuring your team heads in the right direction together. I’m thrilled I got to learn Richard’s perspective and believe other leaders can benefit from hearing it, so I shared the video below. My "challenge question" to other startup leaders is this: what are you doing to foster this type of culture in your organization? Either share below or, feel free to DM me. #semiconductorindustry #startup #leadership

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Good analysis and overview of the supply and demand history from chip manufacturing to HPC products to the end customers.

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Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. Read this blog to learn more about Verilog-A, the most used language by analog designers to describe analog circuit behavior, representing a high-level abstraction of a semiconductor device. https://ow.ly/Opg850Roc20

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TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025 💡 In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, #TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC #N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025. TSMC states that 'N2 development is well on track and #N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb #SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production. Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eHgpfX4k #semiconductormanufacturing #semiconductors #semiconductor #tech #technology #innovation #chip #chips #integratedcircuits #ic #foundry #taiwan #geopolitics #asml #thenetherlands #europe #euv #computer

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Recently, there has been a lot of discussion about TSMC's advanced packaging . Let us provide an in-depth introduction to the packaging of this foundry giant through their financial reports and the latest technology summit . Information shows that after Zhang Zhongmou returned to the company in 2011, he made up his mind to do advanced packaging . Yu Zhenhua, who joined the company in 1994, is the leader of this "secret" project of TSMC. CoWoS technology is TSMC's small test in this field. Their technology was first implemented on Xilinx FPGAs , and the InFO packaging derived from this has shined on Apple processors, and has since made TSMC's packaging famous all over the world. Popular science on TSMC’s advanced packaging technology According to Semiwiki, last year, TSMC merged their 2.5D and 3D packaging products into a single, comprehensive brand 3DFabric. Among them, 2.5D packaging technology CoWoS can be divided into CoWoS and InFO series. First look at CoWoS technology, which can be divided into the following types: 1. CoWoS -S Chip-on- wafer - on -substrate with silicon interposer for die-to-die redistribution layer (RDL) connections is celebrating its big break 10th year of series manufacturing. 2. CoWoS -R The CoWoS -R option replaces the (expensive) silicon interposer spanning the 2.5D die placement area with an organic substrate interposer. The trade-off with CoWoS-R is the smaller line spacing of the RDL interconnects—for example, 4 micron spacing on organic compared to the submicron spacing of CoWoS-S. 3. CoWoS -L Between Silicon -S and Organic-R interposer options, the TSMC CoWoS family includes a newer product with a “native” silicon bridge for (ultra-short distance) interconnect between adjacent die edges. These silicon wafers are embedded in an organic substrate and provide high-density USR connections (with tight L/S spacing) as well as interconnect and power distribution capabilities to (thick) wires and planes on the organic substrate. Note that CoWoS is designated as a "chip last" assembly process, with the chip attached to a fabricated interposer. Maximum package size and RDL enhancement CoWoS -S: 3X reticle (certified in 2021); CoWoS -R: 45X mask (3X in 2022), 4 RDL layers on organic substrate (W/S: 2um/2um), using SoC + 2 HBM 2 die stack for reliability certification; CoWoS -L: 1.5X reticle size reliability evaluation test tool with 4 local interconnect bridges between 1 SoC and 4 HBM 2 chip stacks; InFO _oS: 5X reticle (51mm x 42mm on 110mm x 110mm package ), 5 RDL layers (W/S: 2um/2um), currently under reliability evaluation; #business #india #china #europe #buy #globalbusiness #headhunter #usa #automotive #automotiveindustry #leadership #motivation #kindness #bestadvice #personaldevelopment #linkedin #hiring #careers #help #employment #happiness #jobs #health #global #world #jobchange #process #plasma #Knlowledgestudy #buyer #globalbusiness #Technology #recycle

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Good article on the top two chip manufacturers.

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Cerebras Systems - Pioneering Wafer-Scale AI Computing (2 min read) Cerebras Systems, based in Sunnyvale, CA, is pioneering a new class of computer systems to accelerate AI by orders of magnitude. The company was founded in 2015 and is led by CEO Andrew Feldman, a seasoned Silicon Valley entrepreneur who previously co-founded and led SeaMicro (acquired by AMD for $357 million) and had roles at companies like Force10 Networks and Riverstone Networks. At the core of Cerebras' solution is the Wafer Scale Engine (WSE), the largest chip ever built with 2.6 trillion transistors. The WSE powers systems like the CS-2, enabling breakthroughs across industries. Major customers include TotalEnergies in energy, GlaxoSmithKline, and AstraZeneca in pharma, the Mayo Clinic for medical AI, and national labs like Argonne and Lawrence Livermore. Cerebras has around 335 employees but a major industry impact, with customer commitments approaching $1 billion. With over 400,000 AI cores, massive memory bandwidth, and ultra-fast interconnects, the CS-2 delivers cluster-scale performance in a single system. This allows for cutting training times from months to minutes on complex workloads like seismic modeling, drug discovery, and COVID research. Key verticals are pharmaceuticals/healthcare, energy/industrial, scientific research, and AI/ML. Cerebras removes current hardware constraints, allowing researchers to explore novel architectures and drive previously impossible innovations. As AI complexity grows, wafer-scale computing solutions like those developed by Cerebras Systems may be increasingly important in accelerating AI workloads and enabling new innovations across various industries. Credit: Jeffrey Cooper & Perplexity.ai For more on AI, robots, and Semicon, check out my blog: https://lnkd.in/eWESid86  

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🌟 Elevate Your Semiconductor Team with Top Talent! 🌟 Are you in the semiconductor industry and seeking to strengthen your team with top-tier talent? Look no further! Our expert semiconductor direct hire recruiting services with NSOURCE at WGNSTAR are tailored to match your company's unique needs and propel your business to new heights. With a deep understanding of the intricacies of the semiconductor field, we specialize in identifying and attracting highly skilled professionals who possess the technical prowess and innovative mindset necessary to thrive in this dynamic industry. Here's why partnering with NSOURCE for your semiconductor direct hire needs is a game-changer: Industry Expertise: Our team comprises seasoned recruiters with a comprehensive understanding of the semiconductor landscape, enabling us to pinpoint candidates with the precise skills and experience you require. Extensive Network: Leveraging our vast network of industry connections and proprietary database, we access a pool of talent that may not be readily available through traditional channels, ensuring you have access to the best candidates in the market. Tailored Approach: We understand that every company has unique requirements and culture. That's why we take a personalized approach to recruitment, aligning our efforts with your specific goals and values to find candidates who not only possess the right skills but also fit seamlessly into your organization. Efficiency and Timeliness: Time is of the essence in the fast-paced semiconductor industry. Our streamlined recruitment process is designed to deliver results swiftly, allowing you to fill critical positions without delay and maintain your competitive edge. Long-Term Partnerships: We're not just here to fill a vacancy; we're committed to fostering long-term partnerships that drive your success. By understanding your strategic objectives, we can assist in building a robust team that propels your company toward its goals. Don't settle for mediocre talent when you can have the best. Let us be your trusted partner in semiconductor direct hire recruitment, and together, we'll take your team to the next level of excellence. Connect with us today to discuss how we can support your recruitment needs and empower your semiconductor business for sustained growth and innovation. Your success starts with the right people, and we're here to help you find them! #Recruiting #Hiring #NSOURCE #WGNSTAR #Semiconductor #Recruitment #DirectHire #TalentAcquisition #TechIndustry 🚀✨

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https://lnkd.in/gYhWNvJ5 TSMC won Google, Qualcomm 3nm orders away from Samsung Foundry as the latter struggles with yield and power efficiency issues. South Korea media noting 7 major firms have chosen TSMC 3nm: Nvidia, MediaTek, Intel, Apple, AMD. Google’s 4th gen Tensor processor was made by Samsung Foundry, but the 5th gen will be made on TSMC 3nm. Samsung aims to dramatically improve power efficiency at 2nm via Backside Power Delivery (BSPDN) technology and has sped up 2nm development to next year or 2026 from 2027. Samsung Foundry’s 1st generation 3nm with GAA has had yield and power efficiency troubles, with Samsung’s own Exynos 2500 smartphone processor seeing disappointing yields. Power efficiency and heat management have become keys to winning AI clients. #Semiconductorindustry #electronics #semiconductor #technology #innovation #business #supplychain #engineering #manufacturing #computerchips #semiconductors #chips #chipmaker #foundry credit: business korea

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Hardware is hard (part umpteen) RestOfWorld: "TSMC’s debacle in the American desert. Missed deadlines and tension among Taiwanese and American coworkers are plaguing the chip giant’s Phoenix expansion." "Bruce would be working as a semiconductor engineer. The recruiter explained that he would first spend more than a year in Taiwan learning the ins and outs of the complex chipmaking process. Then, he’d return to Arizona. "But over the next two years, Bruce came to realize that the reality of working at TSMC wasn’t exactly what he had envisioned. While working on nanometer-level processes to make state-of-the-art chips, he struggled with language barriers, long hours, and a strict hierarchy. Bruce soon began second-guessing what he had signed up for. The plant, which was originally set to begin operating in 2024, fell woefully behind schedule; production at the facility is now set to start in 2025. Bruce, who said he signed a confidentiality agreement with TSMC, requested anonymity for this story. He wasn’t the only one disappointed with TSMC’s progress in Arizona — other U.S. workers who spoke to Rest of World echoed Bruce’s concerns. In the past two years, the company has relocated hundreds of Taiwanese workers and their families to Arizona. Instead of a gleaming new facility, these workers found an active construction site, and a company struggling to bridge Taiwanese and American professional and cultural norms. Over the past four months, Rest of World spoke with more than 20 current and former TSMC employees — from the U.S. and Taiwan — at the Arizona plant. All of them requested anonymity because they were not authorized to speak to the media or because they feared retaliation from the company. In February, Rest of World traveled to Phoenix to visit the growing TSMC complex and spend time with the nascent community of transplanted Taiwanese engineers. The American engineers complained of rigid, counterproductive hierarchies at the company; Taiwanese TSMC veterans described their American counterparts as lacking the kind of dedication and obedience they believe to be the foundation of their company’s world-leading success. Some 2,200 employees now work at TSMC’s Arizona plant, with about half of them deployed from Taiwan. While tension at the plant simmers, TSMC has been ramping up its investments, recently securing billions of dollars in grants and loans from the U.S. government. Whether or not the plant succeeds in making cutting-edge chips with the same speed, efficiency, and profitability as facilities in Asia remains to be seen, with many skeptical about a U.S. workforce under TSMC’s army-like command system. “[The company] tried to make Arizona Taiwanese,” G. Dan Hutcheson, a semiconductor industry analyst at the research firm TechInsights, told Rest of World. “And it’s just not going to work.” RestOfWorld: https://lnkd.in/gzDCWJsu #semicomconductors #tsmc

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Well put Kurt Busch. It doesn't seem well understood that deep learning is the killer tool for both application outcomes delivered on servers like OpenAI, and physical-to-digital interface on terminal devices with a variety of input and output modalities including sight, sound, motion, touch, environment (temperature, pressure, moisture, ....), radar, lidar, bio (EMG, EEG, ....) etc.. Battery-powered devices with deep learning sensory understanding are the next architectural step beyond plain signal transport. However, developmental and device economics must remain in acceptable envelopes -- nobody will pay $500 for a glass break sensor no matter how great. And the deep learning models must deliver production performance -- nobody will pay a red cent for a glass break sensor that mistakes any sharp sound for a window breaking. Cost-effective, high-performance deep learning electronics and production off-the-shelf and customized models are the central technology for the next wave of terminals from earbuds to automobiles to satellites.

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