Sandeep Shukla

Cyber physical systems are characterized by continuous interaction between digital control systems and physical systems. To design critical control software that is to be used in control systems, a model-driven correct-by-construction approach is preferable. Modeling languages based on synchronous model of time -- such as Simulink, State Chart, Esterel, Lustre etc., are often used for sequential software synthesis and languages with a polychronous timing model such as Signal, MRICDF… Show more

Cyber physical systems are characterized by continuous interaction between digital control systems and physical systems. To design critical control software that is to be used in control systems, a model-driven correct-by-construction approach is preferable. Modeling languages based on synchronous model of time -- such as Simulink, State Chart, Esterel, Lustre etc., are often used for sequential software synthesis and languages with a polychronous timing model such as Signal, MRICDF (Multi-Rate Instantaneous Channel-connected Data Flow) etc., are often used for concurrent software synthesis. The interfaces of such software to the real world are through digital signals that are often sampled quantities of physical entities -- such as velocity, acceleration, pressure etc. Standard type systems available in programming or modeling languages assign traditional data types such as float, real etc., to these signals. Modelers might mistakenly connect two signals with the same traditional data types but representing different physical entities leading to critical bugs in the synthesized software. Early detection of such mistakes require enhanced type system and type checking algorithms. In this work, we attempt to extend the type system of the polychronous modeling language MRICDF and propose type inference techniques that consider the physical dimensions and units of the signals along with the data types. We also propose an SMT (Satisfiability Modulo Theories) based verification approach that verifies type consistency and provides invariants under which the type consistency is upheld. Show less

Embedded software systems respond to multiple events coming from various sources - some temporally regular (ex: periodic sampling of continuous time signals) and some intermittent (ex: interrupts, exception events etc.). Timely response to such events while executing complex computation, might require multi-threaded implementation. For example, overlapping I/O of various types of events, and computation on such events may be delegated to different threads. However, manual programming of… Show more

Embedded software systems respond to multiple events coming from various sources - some temporally regular (ex: periodic sampling of continuous time signals) and some intermittent (ex: interrupts, exception events etc.). Timely response to such events while executing complex computation, might require multi-threaded implementation. For example, overlapping I/O of various types of events, and computation on such events may be delegated to different threads. However, manual programming of multi-threaded programs is error-prone, and proving correctness is computationally expensive. In order to guarantee safety of such implementations, we believe that a correct-by-construction synthesis of multi-threaded software from formal specification is required. It is also imperative that the multiple threads are capable of making progress asynchronous to each other, only synchronizing when shared data is involved or information requires to be passed from one thread to other. Especially on a multi-core platform, lesser the synchronization between threads, better will be the performance. Also, the ability of the threads to make asynchronous progress, rather than barrier synchronize too often, would allow better real-time schedulability. In this work, we describe our technique for multi-threaded code synthesis from a variant of the polychronous programming language SIGNAL, namely MRICDF. Through a series of experimental benchmarks we show the efficacy of our synthesis technique. Our tool EmCodeSyn which was built originally for sequential code synthesis from MRICDF models has been now extended with multi-threaded code synthesis capability. Our technique first checks the concurrent implementability of the given MRICDF model. For implementable models, we further compute the execution schedule and generate multi-threaded code with appropriate synchronization constructs so that the behavior of the implementation is latency equivalent to that of the original MRICDF model. Show less

FINAL TECHNICAL REPORT

Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise… Show more

Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how integrating a Satisfiability Modulo Theory (SMT) solver to POLYCHRONY compiler can enhance its decision making capabilities. Further, we show, how a polyhedral analysis library integrated to the compiler, can compute safe operational boundaries, and filter unsafe input combinations to keep the system safe. We enhanced the POLYCHRONY compiler’s ability to make more accurate decisions and to accept and characterize the safe input range for specifications where safety may be violated for a relatively small region of a large input space. The enhancement also allows the user to consider the severity of the violation with respect to entire space of inputs, and either reject a specification or synthesize a wrapped software with guaranteed safe operation. Show less

The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today's general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC's discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC… Show more

The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today's general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC's discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC reference implementation, our threading model is capable of executing in parallel on the large number of simple processing units available on GPUs. Our simulation infrastructure is called SCGPSim and it includes a source-to-source (S2S) translator to transform synthesizable SystemC models into parallelly executable programs targeting an NVIDIA GPU. The translator retains the simulation semantics of the original designs by applying semantics preserving transformations. The resulting transformed models mapped onto the massively parallel architecture of GPUs improve simulation efficiency quite substantially. Preliminary experiments with varying-sized examples such as AES, ALU, and FIR have shown simulation speed-ups ranging from 30x to 100x. Considering that our transformations are not yet optimized, we believe that optimizing them will improve the simulation performance even further. Show less

Invited Paper

Abstract: Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of… Show more

Invited Paper

Abstract: Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of multiple central processing units, and multiple co-processors such as GPUs. This has peaked an interest in parallelizing SystemC simulations. Of these, several efforts focus on utilizing the massive parallelism offered by GPUs as an alternate computing platform. In this paper, we present a summary of these recent research efforts that propose using GPUs for accelerating SystemC simulation. Show less

Synthesis of application specific hardware which minimizes area while not sacrificing latency or clock speed is a much researched problem. In most of the past works, the hardware is described structurally in hardware description languages with behaviors attached to structures. Since the structure is manually decided, the architect has to decide whether certain components can be reused without increasing latency. For example, if one can prove that certain behaviors never happen at the same time,… Show more

Synthesis of application specific hardware which minimizes area while not sacrificing latency or clock speed is a much researched problem. In most of the past works, the hardware is described structurally in hardware description languages with behaviors attached to structures. Since the structure is manually decided, the architect has to decide whether certain components can be reused without increasing latency. For example, if one can prove that certain behaviors never happen at the same time, these behaviors can be mapped to common components, with a simple control state machine determining which behavioral mode the behavior belongs to. Since application specific hardware are used as co-processors for performance boost, and such computations are best described as a data-flow computation, we choose a high level data-flow oriented formal specification language, and use a new semantic model for this specification language, namely conditional partial order graphs. The advantage of our approach is that our specification language MRICDF is graphical, polychronous, has formal semantics, and hence synthesizing its control structure into conditional partial order is a natural fit. Additionally, the specific calculus of constraints in polychronous languages -- namely clock calculus, and associated analysis with Boolean theory of prime implicates, and constraint satisfiability checking with SMT solvers provide us with a natural way of discovering behaviors that belong to disjoint modes, and thereby allow us to reuse components with simple micro-instruction set synthesis. In this paper, we show how MRICDF can be used to formally synthesize such application specific instruction processors. Show less

The advent of microgrids has made possible a host of applications geared toward the enhancement of the efficiency, reliability, resiliency, and sustainability of an electric power system. With a large penetration of microgrids in a power distribution system, a dedicated communication network infrastructure is needed to coordinate their control actions under various system operating conditions. This paper evaluates the ability of the current wireless communication infrastructure to meet some… Show more

The advent of microgrids has made possible a host of applications geared toward the enhancement of the efficiency, reliability, resiliency, and sustainability of an electric power system. With a large penetration of microgrids in a power distribution system, a dedicated communication network infrastructure is needed to coordinate their control actions under various system operating conditions. This paper evaluates the ability of the current wireless communication infrastructure to meet some specific requirements and proposes some remedial actions. To this end, we have implemented communications models on the OPNETTM simulation tool and have investigated the impacts of latency and packet losses on the ability of microgrids’ responses to some disturbances in the main grid. We found that the communications infrastructure must implement suitable channel access mechanisms for wireless transmission and must also support differentiated services to accommodate the variety of traffic patterns generated by the microgrids’ control actions. If there are no differentiated services like the AQM, the performance of the controllers degrades Show less