Vtool - Smart Verification

Vtool - Smart Verification

Semiconductor Manufacturing

Tel Avivi, Israel 4,154 followers

Building Cogita Visual Debug, bringing back the power of visual interpretation to the ASIC verification process.

About us

Vtool answers to the ever-increasing need for faster, more reliable ASIC and FPGA development cycles. Headquartered in Israel, and operating out of France, Serbia, Poland, Greece, and India, Vtool is an EDA verification company, a RISC-V SoC adaptable platform provider, and an ASIC and embedded SW design house. It synergizes between these three key pillars and offers flexible engagement models with a global outreach. Its advanced EDA tool, Cogita-PRO, is a first-of-its-kind debug platform that ensures first-time-right silicon by applying advanced AI-based verification analytics; Vtool's modular and easily adaptable RISC-V SoC framework, Universa, is an integrated HW/SW ready-to-use core that gives a head-start for developing SoC solutions faster; and its HW/SW consulting services cover the entire ASIC design, verification, embedded SW, and analog/RF design that provides customers with a clear path to success. At its core, Vtool promotes a people-oriented philosophy of technology, opening up a unique space for diverse perspectives and creative innovation. It is renowned for its knowledge-sharing community and ongoing guided training, including long-term academic involvement in leading European universities. Established in 2014, Vtool is led by industry experts with a proven track record, and its team of more than 150 professionals is growing rapidly as a powerhouse for stronger, faster verification that serves chipmakers worldwide.

Website
http://thevtool.com
Industry
Semiconductor Manufacturing
Company size
51-200 employees
Headquarters
Tel Avivi, Israel
Type
Privately Held
Founded
2014
Specialties
Verification, chip design, Semiconductors, Asic Verification, FPGA Verification, EDA, SystemVerilog, UVM, debug, log, VLSI, SOC, debbuger, and specman

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Employees at Vtool - Smart Verification

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